Page History
...
Following table shows on-board board Silicon Labs I2C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:
Si5345A Pin | Signal Name / Description | Connected To | Direction | Note |
---|
IN0 |
IN0_ |
PLL clock generator U17
IN3
IN4
Reference input clock
IN5
IN6-
CLK0A
CLK0BSSD_RCLK_P
NGFF M.2 PCIe socket (Key M),
dedicated as SSD interface
PS GTR Bank 505 Lane 2, dedicated for DisplayPort
PS GTR Bank 505 Lane 1, dedicated for USB3 interface
B505_CLK0_P
PS GTR Bank 505 Lane 0, dedicated for SSD interface
...
P | not connected | Input | Not used | |
IN0_N | GND | |||
IN1 | IN1_P | SMA Coax J25, pin 1 | Input | external reference clock input |
IN1_N | GND | |||
IN2 | - | not connected | Input | not used |
- | not connected | |||
IN3 | - | not connected | Input | not used |
- | not connected | |||
OUT0 | CLK0_P | not connected | Output | not used |
CLK0_N | not connected | |||
OUT1 | CLK1_P | U1, pin E8 | Output | GTH bank 229 reference clock input |
CLK1_N | U1, pin E7 | |||
OUT2 | CLK2_P | U1, pin B10 | Output | GTH bank 230 reference clock input |
CLK2_N | U1, pin B9 | |||
OUT3 | CLK3_P | U1, pin J8 | Output | GTH bank 228 reference clock input |
CLK3_N | U1, pin J7 | |||
OUT4 | CLK4_P | U1, pin N27 | Output | GTH bank 128 reference clock input |
CLK4_N | U1, pin N28 | |||
OUT5 | CLK5_P | U1, pin J27 | Output | GTH bank 129 reference clock input |
CLK5_N | U1, pin J28 | |||
OUT6 | CLK6_P | U1, pin E27 | Output | GTH bank 130 reference clock input |
CLK6_N | U1, pin E28 | |||
OUT7 | CLK7_P | U27, pin E1 | Output | Clock signal input to SC CPLD, bank 5 |
CLK7_N | not connected | |||
OUT8 | CLK8_P | U12, pin 2 | Output | Differential reference clock input to |
CLK8_N | U12, pin 1 | |||
OUT9 | - | not connected | Output | not used |
- | not connected | |||
XA/XB | XAXB_P | 54.000 MHz quartz oscillator Y1 | Input | Differential quartz oscillator clock input |
XAXB_N |
Table 52: Programmable 10-output PLL clock generator inputs and outputs
Note: The PLL clock generator U17 can be reseted by the pin 'PLL_RST', which is connected to SC CPLD U27, bank 4 pin L4 with low active logic.
On-board LEDs
The TEB0911 board is equipped with several LEDs to signal current states and activities.
LED | Color | Connected to | Description and Notes |
---|---|---|---|
D1D6 | Green | ||
.. | .. | .. | .. |
Table 53: On-board LEDs
...
red | Zynq MPSoC U1, pin W21 | Reflects inverted DONE signal. ON when FPGA is not configured, | |
D17 | green | USB3 Hub U4, pin 25 | LED is on if all USB3 and USB2 ports are in the suspend state and is |
D18 | green | USB3 Hub U4, pin 4 | LED output for downstream 1 port |
D19 | green | USB3 Hub U4, pin 63 | LED output for downstream 3 port |
D2 | red | SC CPLD U27, bank 2, pin AB17 | SFP+ interface status LED |
D4 | green | SC CPLD U27, bank 2, pin AB18 | SFP+ interface status LED |
D3 | red | SC CPLD U27, bank 2, pin AA16 | SFP+ interface status LED |
D5 | green | SC CPLD U27, bank 2, pin AB15 | SFP+ interface status LED |
D13 | green | SC CPLD U27, bank 2, pin U12 | functionality depends on the current firmware of the SC CPLD U27 |
D14 | green | SC CPLD U27, bank 2, pin V12 | |
D15 | green | SC CPLD U27, bank 2, pin W12 | |
D1 | red | SC CPLD U27, bank 2, pin V13 |
Table 53: On-board LEDs
User Buttons
There are two switch buttons available to the user connected to the SC CPLD U27:
Button | Color | Connected to | Description and Notes |
---|---|---|---|
D6 | red | Zynq MPSoC U1, pin W21 | Reflects inverted DONE signal. ON when FPGA is not configured, |
D17 | green | USB3 Hub U4, pin 25 | LED is on if all USB3 and USB2 ports are in the suspend state and is |
D2 | red | SC CPLD U27, bank 2, pin AB17 | SFP+ interface status LED |
D4 | green | SC CPLD U27, bank 2, pin AB18 | SFP+ interface status LED |
D3 | red | SC CPLD U27, bank 2, pin AA16 | SFP+ interface status LED |
D5 | green | SC CPLD U27, bank 2, pin AB15 | SFP+ interface status LED |
D13 | green | SC CPLD U27, bank 2, pin U12 | functionality depends on the current firmware of the SC CPLD U27 |
D14 | green | SC CPLD U27, bank 2, pin V12 | |
D15 | green | SC CPLD U27, bank 2, pin W12 | |
D1 | red | SC CPLD U27, bank 2, pin V13 |
Configuration DIP-switches
...