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Following table shows on-board board Silicon Labs I²C programmable Si5345A U17 10-output programmable PLL reference clock generator inputs and outputs:

Si5345A Pin	Signal Name / Description	Connected To	Direction	Note

IN1CLK8

IN0

IN2

IN0_

NU17, pin 54InputDifferential reference clock input from
PLL clock generator U17CLK8_PU17, pin 53Input

IN3

IN4

Reference input clock

U85, pin 3Input25.000000 MHz oscillator, Si8008AI-GNDInputI²C slave device address LSB

IN5

IN6

-

Not connectedInputNot used-GNDInputNot used

CLK0A

CLK0B

SSD_RCLK_P

U2, pin 55Output

NGFF M.2 PCIe socket (Key M),
dedicated as SSD interface

SSD_RCLK_NU2, pin 53OutputCLK1ACLK1BB505_CLK2_NU1, pin U27Output

PS GTR Bank 505 Lane 2, dedicated for DisplayPort

B505_CLK2_PU1, pin U28OutputCLK2ACLK2BB505_CLK1_NU1, pin W27Output

PS GTR Bank 505 Lane 1, dedicated for USB3 interface

B505_CLK1_PU1, pin W28OutputCLK3ACLK3B

B505_CLK0_P

U1, pin AA27Output

PS GTR Bank 505 Lane 0, dedicated for SSD interface

B505_CLK0_NU1, pin AA28OutputInputConnected toFrequencyNotesIN0On-board Oscillator U1825.000000 MHz-IN1B2B Connector pins J2-3, J2-1 (differential pair)UserAC decoupling required on baseIN2B2B Connector pins J3-66, J3-68 (differential pair)UserAC decoupling required on baseIN3OUT9UserLoop-back from OUT9OUT0B2B Connector pins J2-3, J2-1 (differential pair)UserDefault offOUT1B230 CLK0UserDefault offOUT2B229 CLK1UserDefault offOUT3B228 CLK1UserDefault offOUT4B505 CLK2UserDefault offOUT5B505 CLK3UserDefault offOUT6B128 CLK0UserDefault offOUT7B2B Connector pins J2-7, J2-9 (differential pair)UserDefault offOUT8B2B Connector pins J2-13, J2-15 (differential pair)UserDefault offOUT9IN3 (Loop-back)UserDefault offXA/XBQuartz (Y1)50.000 MHz-

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P	not connected	Input	Not used
IN0_N	GND
IN1	IN1_P	SMA Coax J25, pin 1	Input	external reference clock input
	IN1_N	GND
IN2	-	not connected	Input	not used
	-	not connected
IN3	-	not connected	Input	not used
	-	not connected
OUT0	CLK0_P	not connected	Output	not used
	CLK0_N	not connected
OUT1	CLK1_P	U1, pin E8	Output	GTH bank 229 reference clock input
	CLK1_N	U1, pin E7
OUT2	CLK2_P	U1, pin B10	Output	GTH bank 230 reference clock input
	CLK2_N	U1, pin B9
OUT3	CLK3_P	U1, pin J8	Output	GTH bank 228 reference clock input
	CLK3_N	U1, pin J7
OUT4	CLK4_P	U1, pin N27	Output	GTH bank 128 reference clock input
	CLK4_N	U1, pin N28
OUT5	CLK5_P	U1, pin J27	Output	GTH bank 129 reference clock input
	CLK5_N	U1, pin J28
OUT6	CLK6_P	U1, pin E27	Output	GTH bank 130 reference clock input
	CLK6_N	U1, pin E28
OUT7	CLK7_P	U27, pin E1	Output	Clock signal input to SC CPLD, bank 5
	CLK7_N	not connected
OUT8	CLK8_P	U12, pin 2	Output	Differential reference clock input to PLL clock generator U12
	CLK8_N	U12, pin 1
OUT9	-	not connected	Output	not used
	-	not connected
XA/XB	XAXB_P	54.000 MHz quartz oscillator Y1	Input	Differential quartz oscillator clock input
	XAXB_N

Table 52: Programmable 10-output PLL clock generator inputs and outputs

Note: The PLL clock generator U17 can be reseted by the pin 'PLL_RST', which is connected to SC CPLD U27, bank 4 pin L4 with low active logic.

On-board LEDs

The TEB0911 board is equipped with several LEDs to signal current states and activities.

LED	Color	Connected to	Description and Notes
D1D6	Green
..	..	..	..

Table 53: On-board LEDs

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red	Zynq MPSoC U1, pin W21	Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL configuration is finished.
D17	green	USB3 Hub U4, pin 25	LED is on if all USB3 and USB2 ports are in the suspend state and is off when one of the ports comes out of the suspend state.
D18	green	USB3 Hub U4, pin 4	LED output for downstream 1 port
D19	green	USB3 Hub U4, pin 63	LED output for downstream 3 port
D2	red	SC CPLD U27, bank 2, pin AB17	SFP+ interface status LED
D4	green	SC CPLD U27, bank 2, pin AB18	SFP+ interface status LED
D3	red	SC CPLD U27, bank 2, pin AA16	SFP+ interface status LED
D5	green	SC CPLD U27, bank 2, pin AB15	SFP+ interface status LED
D13	green	SC CPLD U27, bank 2, pin U12	functionality depends on the current firmware of the SC CPLD U27
D14	green	SC CPLD U27, bank 2, pin V12
D15	green	SC CPLD U27, bank 2, pin W12
D1	red	SC CPLD U27, bank 2, pin V13

Table 53: On-board LEDs

User Buttons

There are two switch buttons available to the user connected to the SC CPLD U27:

Button	Color	Connected to	Description and Notes
D6	red	Zynq MPSoC U1, pin W21	Reflects inverted DONE signal. ON when FPGA is not configured, OFF as soon as PL configuration is finished.
D17	green	USB3 Hub U4, pin 25	LED is on if all USB3 and USB2 ports are in the suspend state and is off when one of the ports comes out of the suspend state.
D2	red	SC CPLD U27, bank 2, pin AB17	SFP+ interface status LED
D4	green	SC CPLD U27, bank 2, pin AB18	SFP+ interface status LED
D3	red	SC CPLD U27, bank 2, pin AA16	SFP+ interface status LED
D5	green	SC CPLD U27, bank 2, pin AB15	SFP+ interface status LED
D13	green	SC CPLD U27, bank 2, pin U12	functionality depends on the current firmware of the SC CPLD U27
D14	green	SC CPLD U27, bank 2, pin V12
D15	green	SC CPLD U27, bank 2, pin W12
D1	red	SC CPLD U27, bank 2, pin V13

Configuration DIP-switches

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On-board LEDs

User Buttons

Configuration DIP-switches