Page History
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| FMC | Interfaces | I/O Signal Count | LVDS-pairs count | Connected to | VCCO bank Voltage | Notes |
|---|---|---|---|---|---|---|
J10 (FMC A) | I/O | 12 | 6 | Bank 44 HD | FMCAF_1V8 | - |
| 46 | 28 | SC CPLD U27 Bank 1 | FMCAF_1V8 | - | ||
| I²C | 2 | - | I²C-Switch U37 | - | Muxed to MIO Bank 501 I²C Inteface | |
| JTAG | 4 | - | SC CPLD U27 Bank 2 | 3.3VSB | - | |
| MGT | - | 8 (4 x RX/TX) | Bank 128 GTH | - | 4x MGT lanes | |
| Clock Input | - | 1 | Bank 128 GTH | - | 1x Reference clock input to MGT bank | |
| Control Signals | 3 | - | SC CPLD U27 Bank 0 | 3.3VSB | 'FMCA_PG_C2M', 'FMCA_PG_M2C', 'FMCA_PRSNT' |
Table 3: FMC A connector interfaces
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For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.
The PS_1V8 and VCCINT_0V85 voltage levels are monitored by the voltage monitor circuit U89, which generates the POR_B signal to reset the board if voltage failure occurs. A manual resetis also possible by driving the pin 'MR' on SC CPLD, bank 4, pin L7 to GND. Refer to documentation of the SC CPLD firmware for detailed information to reset the board manually.
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| MIO | Signal Name | U24 Pin | MIO | Signal Name | U25 Pin | MIO | Signal Name | U25 U26 Pin | ||
|---|---|---|---|---|---|---|---|---|---|---|
| 0 | SPI Flash CLK | B2 | 7 | SPI Flash CS | C2 | 13 | MMC D0 | H3 | ||
| 1 | SPI Flash IO1 | D2 | 8 | SPI Flash IO0 | D3 | 14 | MMC D1 | H4 | ||
| 2 | SPI Flash IO2 | C4 | 9 | SPI Flash IO1 | D2 | 15 | MMC D2 | H5 | ||
| 3 | SPI Flash IO3 | D4 | 10 | SPI Flash IO2 | C4 | 16 | MMC D3 | J2 | ||
| 4 | SPI Flash IO0 | D3 | 11 | SPI Flash IO3 | D4 | 17 | MMC D4 | J3 | ||
| 5 | SPI Flash CS | C2 | 12 | SPI Flash CLK | B2 | 18 | MMC D5 | J4 | ||
| 19 | MMC D6 | J5 | ||||||||
| 20 | MMC D7 | J6 | ||||||||
| 21 | MMC CMD | W5 | ||||||||
| 22 | MMC CLKR | W6 | ||||||||
| 23 | MMC RST | U5 |
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