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TEB0911-

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03 block diagram

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Main Components

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title	Figure 2: TEB0911-03 main components

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Following diagram gives an overview of the FMC connectors and their connections to the Zynq Ultrascale+ MPSoC and the System Controller CPLD U27:

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title	Figure x3: General overview of the FMC connectors

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<!-- MGT lanes should be listed separately, as they are more specific than just general I/Os. -->

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JTAG access to the Zynq MPSoC and SC CPLD is provided through XMOD header J24 and J35. :

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title	Figure 4: XMOD header J24 and J35

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6Figure X: XMOD header J24 and J35
Signal Assignment of XMOD header J24 and J35

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On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 IC U20. The Ethernet PHY RGMII interface is connected to the Zynq MPSoC Ethernet interface of the PS MIO bank 502. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from the on-board 25.000000 MHz oscillator U21. The LEDs of the RJ-45 MegJack J13 are connected to the System Controller CPLD bank 2, pins Y12, Y13 and Y14.

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title	Figure 5: Gigabit Ethernet interface

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PHY Pin	Connected to	Notes
MDC/MDIO	PS bank 502 MIO76, MIO77	-
PHY LED0..2	SC CPLD U27, bank 4, pin L5, L1, K1	see schematic for details, forwarded to RJ45 GbE MagJack J7
PHY_CLK125M	SC CPLD U27, bank 4, pin K2	125 MHz Ethernet PHY clock out
CONFIG	pulled up to PS_1V8	Configuration of PHY address LSB and VDDO level
RESETn	SC CPLD U27, bank 4, pin L6	Active low reset line
RGMII	PS bank 502 MIO64 ... MIO75	Reduced Gigabit Media Independent Interface
SGMII	-	Serial Gigabit Media Independent Interface
MDI	RJ45 GbE MagJack J13	Media Dependent Interface

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On the TEB0911 board two USB3 Superspeed ports are available to the user, which are downward compatible to USB2 Highspeed.

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title	Figure 6: USB3 interface

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2Figure X: USB3 interface
The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

IC	Interface	Signal Schematic Names	Connected to	Note
USB3 Hub U4	USB3 Upstream MGT lane	B505_TX1_P B505_TX1_N B505_RX1_P B505_RX1_N	PS GTR bank 505 Pins: PS_MGTRTXP1_505, Y29 PS_MGTRTXN1_505, Y30 PS_MGTRRXP1_505, AA31 PS_MGTRTXN1_505, AA32	-
	USB2 Uptream data LVDS pair	USB0_D_P USB0_D_N	USB2 PHY U15 Pins: 18,19	-
	USB3 Downstream lane	USB3_RXDN1_D_P USB3_RXDN1_D_N USB3_TXDN1_D_P USB3_TXDN1_D_N USB3_RXDN2_D_P USB3_RXDN2_D_N USB3_TXDN2_D_P USB3_TXDN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	USB2 Downstream LVDS pair	USB2_DN1_D_P USB2_DN1_D_N USB2_DN2_D_P USB2_DN2_D_N	2-port USB3 A / RJ-45 connector (stacked) J13	-
	I²C	USBH_SDA USBH_SCL	Configuration EEPROM U5, 8-channel I²C-switch U37	EEPROM U5 is configuration and parameter memory of USB3 hub U4
	Control Lines	USBH_MODE0, USBH_MODE1 USBH_RST	SC CPLD U27, bank 2 Pins: Y17, Y16, Y15	-
USB2 PHY U15	USB2 ULPI	USB0_STP USB0_NXT USB0_DIR USB0_CLK USB0_DATA0 ... USB0_DATA7	PS bank 502 Pins: MIO52 ... MIO63	-
	USB2 data LVDS pair	USB0_D_P USB0_D_N	USB3 Hub U4 Pins: 71,72	-
	Control Lines	USB0_RST	SC CPLD U27, bank 4 Pin: M2	-

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Block diagram below shows the dependencies between the implied devices which establish the SFP+ interface:

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title	Figure 7: SFP+ interface

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Figure X: SFP+ interface

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
SFP+ J9A	MGT Lane	B129_TX3_P B129_TX3_N B129_RX3_P B129_RX3_N	GTH bank 129 Pins: MGTHTXP3_129, G31 MGTHTXN3_129, G32 MGTHRXP3_129, F33 MGTHRXN3_129, F34	BiDir	Multi gigabit highspeed data lane	-	-
	I²C	SFP0_SDA SFP0_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface	-	-
	Control Lines	SFP0_RS0	I²C 8-bit I/O Port-Expander U86	Output	Full RX bandwidth	Low active	I/O Port Expander on same I²C line as SFP0-I²C-interface
		SFP0_RS1		Output	Reduced RX bandwidth	Low active
		SFP0_M-DEF0		Input	Module present / not present	Low active
		SFP0_TX_FAULT		Input	Fault / Normal Operation	High active
		SFP0_LOS	SC CPLD U27, bank 2, pin V8	Input	Loss of receiver signal	High active	-
		SFP0_TX_DIS	SC CPLD U27, bank 2, pin Y7	Output	SFP Enabled / Disabled	Low active	-
SFP+ J9B	MGT Lane	B129_TX2_P B129_TX2_N B129_RX2_P B129_RX2_N	GTH bank 129 Pins: MGTHTXP2_129, H29 MGTHTXN2_129, H30 MGTHRXP2_129, H33 MGTHRXN2_129, H34	BiDir	Multi gigabit highspeed data lane	-	-
	I²C	SFP1_SDA SFP1_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface	-	-
	Control Lines	SFP1_RS0	I²C 8-bit I/O Port-Expander U86	Output	Full RX bandwidth	Low active	I/O Port Expander on same I²C line as SFP0-I²C-interface
		SFP1_RS1		Output	Reduced RX bandwidth	Low active
		SFP1_M-DEF0		Input	Module present / not present	Low active
		SFP1_TX_FAULT		Input	Fault / Normal Operation	High active
		SFP1_LOS	SC CPLD U27, bank 2, pin W7	Input	Loss of receiver signal	High active	-
		SFP1_TX_DIS	SC CPLD U27, bank 2, pin V7	Output	SFP Enabled / Disabled	Low active	-

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On the TEB0911 UltraRack board one SSD interface is available provided by a NGFF (Next Generation Form Faktor) M.2 socket (Key M) which supports data transmission rates for PCIe3, SATA3 and USB3 interfaces.

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title	Figure 8: SSD interface

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Figure X: SSD interface

Connector	Interface	Signal Schematic Name	Connected to	FPGA Direction	Description	Logic	Notes
M.2-NGFF PCIe Socket U2	MGT Lane	B505_TX0_P B505_TX0_N B505_RX0_P B505_RX0_N	PS GTR bank 505 Pins: PS_MGTRTXP0_505, AB29 PS_MGTRTXN0_505, AB30 PS_MGTRRXP0_505, AB33 PS_MGTRTXN0_505, AB34	BiDir	Multi gigabit highspeed data lane	-	-
	Clock Input	SSD_RCLK_P SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0	-	Reference clock signal	-	-
	Control Lines	SSD1_LED	SC CPLD U27, bank 2, pin AA13	Output	LED Output	High active	-
		SSD1_SLEEP	SC CPLD U27, bank 2, pin AA12	Input	PCIe sleep state	Low active
		SSD1_PERSTN	SC CPLD U27, bank 2, pin AA11	Input	PCIe reset input	Low active	-
		SSD1_WAKE	SC CPLD U27, bank 2, pin AB11	Input	PCIe Link reactivation	Low active	-
		SSD1_CLKRQ	connect to GND	BiDir	PCIe Clock Request	Low active	-

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The TEB0911 board provides the high speed DisplayPort interface for visual output. The DisplayPort is connected with two transmit LVDS-pairs of bank 505 PS GTR lanes. Additionally the auxiliary transmit line is established by the SC CPLD in conjunction with a LVDS Line Driver/Receiver.

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title	Figure 9: DisplayPort interface

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Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

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On the TEB0911 board there is a DDR4 memory interface with a 64-bit databus width available for SO-DIMM modules.

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title	Figure 10: DDR4 memory interface

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14Figure X: DDR4 memory interface
Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:

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The TEB0911 board provides a CAN interface, the CAN transceiver is connected and operated by the SC CPLD:

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title	Figure 11: CAN interface

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The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:

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The SD Card interface of the TEB0911 board is routed via SD IO interface to the PS MIO bank 501 of the Zynq Ultrascale+ MPSoC (3.3V VCCO). The SC CPLD U27 controls the load switch Q3 to enable the card sockets J11 with signal 'SD_EN', bank 2, pin U11. The "Card Detect" and "Write Protect" signal are also routed to the SC CPLD:

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title	Figure 12: SD Card interface

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6Figure X: SD Card interface
The SD Card socket have following signal and pin assignment:

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The TEB0911 offers 3x 4-wire PWM FAN connectors for optional cooling fans controlled by SC CPLD U27:

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title	Figure 13: 4-wire PWM FAN connectors

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Connector	Signal Schematic Name	Connected to	Notes
Fan Connector J2	F1PWM	SC CPLD U27, bank 0, pin E10	-
	F1SENSE	SC CPLD U27, bank 0, pin D11	-
	F1_EN	SC CPLD U27, bank 0, pin C8	Controls 12V Load Switch
Fan Connector J23	F2PWM	SC CPLD U27, bank 0, pin D9	-
	F2SENSE	SC CPLD U27, bank 0, pin G12	-
	F2_EN	SC CPLD U27, bank 0, pin B4	Controls 12V Load Switch
Fan Connector J33	F3PWM	SC CPLD U27, bank 0, pin B13	-
	F3SENSE	SC CPLD U27, bank 0, pin A13	-
	F3_EN	SC CPLD U27, bank 0, pin A12	Controls 12V Load Switch

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With the SMA Coaxial connector J25 the clock generator can be supplied with an external clock signal.

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title	Figure 14: PLL clock interface

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Connector

Signal Schematic Name

Connected to

Notes

Pin Header

J22

PLL_SCL

clock generator U17, pin 16

PS_1V8 VCCIO

PLL_SDA

clock generator U17, pin 18

SMA Coax

J25

CLK_PLL_IN

clock generator U17, pin 1

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Following block diagram visualizes the connection of the SC CPLDs with the Zynq Ultrascale+ MPSoC via PS MIO pins and singled ended PL pins:

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title	Figure X15: I/O's connecting Zynq MPSoC and SC CPLD

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For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.

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There are following dependencies how the initial 24V voltage from the main power jack J34 is distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

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title	Figure 16: Power distribution diagram

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title	Figure 17: Power distribution diagram continued

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Warning
To avoid any damage to the module, check for stabilized on-board voltages should be carried out(i.e. power good and enable signals) before powering up any SoC's I/O bank voltages VCCO_x. All I/Os should be tri-stated during power-on sequence.

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Following diagram describes the sequence of enabling the three power instances utilizing the DC-DC converter control signals (Enable, Power-Good), which will power-up in descending order as listed in the blocks of the diagram.

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title	Figure 18: Power-On sequence diagram

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Temp core dc

Power Rails

NB! Following table with examples is valid for most of the 4 x 5 cm modules but depending on the module model and specific design, number and names of power rails connected to the B2B connectors may vary.

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Trenz Electronic Documentation

Versions Compared

Old Version 118

New Version 119

Key

Main Components

Power Rails