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| Scroll Title |
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| anchor | Figure 9 |
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| title | Figure 9: DisplayPort interface |
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|
| draw.io Diagram |
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| border | truefalse |
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| viewerToolbar | true |
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| |
|---|
| fitWindow | false |
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| diagramName | DisplayPort interface diagram formatted |
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| simpleViewer | false |
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| width | |
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| links | auto |
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| tbstyle | hidden |
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| lbox | true |
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| diagramWidth | 641 |
|---|
| revision | 2 |
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Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:
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| Scroll Title |
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| anchor | Figure 10 |
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| title | Figure 10: DDR4 memory interface |
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|
| draw.io Diagram |
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| border | truefalse |
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| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
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| diagramName | DDR4 memory interface diagram formatted |
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| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| lbox | true |
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| diagramWidth | 642 |
|---|
| revision | 1 |
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|
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Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:
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| Scroll Title |
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| anchor | Figure 11 |
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| title | Figure 11: CAN interface |
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|
| draw.io Diagram |
|---|
| border | truefalse |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
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| diagramName | CAN interface diagram formatted |
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| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| lbox | true |
|---|
| diagramWidth | 402641 |
|---|
| revision | 12 |
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|
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The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:
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| Scroll Title |
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| anchor | Figure 12 |
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| title | Figure 12: SD Card interface |
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|
| draw.io Diagram |
|---|
| border | truefalse |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramName | SD Card interface diagram formatted |
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| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| lbox | true |
|---|
| diagramWidth | 641 |
|---|
| revision | 1 |
|---|
|
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The SD Card socket have following signal and pin assignment:
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| Scroll Title |
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| anchor | Figure 13 |
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| title | Figure 13: 4-wire PWM FAN connectors |
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|
| draw.io Diagram |
|---|
| border | truefalse |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramName | 4-Wire PWM FAN connectors diagram formatted |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| lbox | true |
|---|
| diagramWidth | 641 |
|---|
| revision | 2 |
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|
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| Connector | Signal Schematic Name | Connected to | Notes |
|---|
Fan Connector J2 | F1PWM | SC CPLD U27, bank 0, pin E10 | - |
| F1SENSE | SC CPLD U27, bank 0, pin D11 | - |
| F1_EN | SC CPLD U27, bank 0, pin C8 | Controls 12V Load Switch |
Fan Connector J23 | F2PWM | SC CPLD U27, bank 0, pin D9 | - |
| F2SENSE | SC CPLD U27, bank 0, pin G12 | - |
| F2_EN | SC CPLD U27, bank 0, pin B4 | Controls 12V Load Switch |
Fan Connector J33 | F3PWM | SC CPLD U27, bank 0, pin B13 | - |
| F3SENSE | SC CPLD U27, bank 0, pin A13 | - |
| F3_EN | SC CPLD U27, bank 0, pin A12 | Controls 12V Load Switch |
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| Scroll Title |
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| anchor | Figure 14 |
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| title | Figure 14: PLL clock interface |
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|
| draw.io Diagram |
|---|
| border | truefalse |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramName | PLL clock interfaces diagram formatted |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| lbox | true |
|---|
| diagramWidth | 641 |
|---|
| revision | 1 |
|---|
|
|
| Connector | Signal Schematic Name | Connected to | Notes |
|---|
Pin Header J22 | PLL_SCL | clock generator U17, pin 16 | PS_1V8 VCCIO
|
| PLL_SDA | clock generator U17, pin 18 |
SMA Coax J25 | CLK_PLL_IN | clock generator U17, pin 1 | - |
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| Scroll Title |
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| anchor | Figure 15 |
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| title | Figure 15: I/O's connecting Zynq MPSoC and SC CPLD |
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|
| draw.io Diagram |
|---|
| border | false |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramName | SC CPLD Zynq MPSoC CPLD connections |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| links | auto |
|---|
| tbstyle | hidden |
|---|
| lbox | true |
|---|
| diagramWidth | 641 |
|---|
| revision | 111 |
|---|
|
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For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.
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