Page History

Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"

Important General Note:

• Export PDF to download, if vivado revision is changed!

• Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

  • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    • Figure template (note: inner scroll ignore/only only with drawIO object):

      Scroll Title
      anchor Figure_xyz title Text
      Scroll Ignore Create DrawIO object here: Attention if you copy from other page, use Scroll Only image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

      
      

    • Table template:

      • Layout macro can be use for landscape of large tables
      • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

    • 
      

      Scroll Title
      anchor Table_xyz title Text
      Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Example Comment 1 2

      
      

• ...

Notes :

• short description of the design

• Short Link of "Scroll only" macro:

  • Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info

  • List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Notes :

• Add basic key features, which can be tested with the design

• Vitis/Vivado 2021.2
• PetaLinux
• MicroBlaze
• I2C
• UART
• Flash
• FMeter
• SI5338 initialisation with MCS

Notes :

• add every update file on the download
• add design changes on description

• add known Design issues and general notes for the current revision
• do not delete known issue, add fixed version time stamp if issue fixed

Notes :

• list of software which was used to generate the design

Notes :

• list of hardware which was used to generate the design
• mark the module and carrier board, which was used tested with an ^*

^*used as reference

^*used as reference

^*used as reference

Notes :

• content of the zip file

Notes :

• prebuilt files
• Template Table:

  • 
    

    Scroll Title
    anchor Table_PF title-alignment center title Prebuilt files
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File Boot Script-File *.scr Distro Boot Script file DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Device Tree *.dts Device tree (2 possible, one for u-boot and one for linux) Hardware-Platform-Description-File *.xsa Exported Vivado hardware description file for Vitis and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

    
    

• Important set new Vivado version link on every Design update of new vivado version!
• Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

• Basic Design Steps

• Add/ Remove project specific description

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

Note:

• Programming and Startup procedure

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Note:

• Add picture of HW Manager

• add notes for the signal either groups or topics, for example:
  

  Control:

  • add controllable IOs with short notes..

  Monitoring:

  • add short notes for signals which will be monitored only
  • SI5338 CLKs:
    • Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz
    • expected CLK Frequency...
      

Note:

• Description of Block Design, Constrains... BD Pictures from Export...

Note:

• optional for Zynq / ZynqMP only

• add basic PS configuration

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 69 [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR YES [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.M1PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M2PIN PULLNONE [current_design]
set_property BITSTREAM.CONFIG.M0PIN PULLNONE [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

set_property PACKAGE_PIN AD28 [get_ports sc0841_interface_ddr4_par_44]
set_property PACKAGE_PIN C28 [get_ports sc0841_interface_ddr4_par_46]
set_property PACKAGE_PIN AD20 [get_ports sc0841_interface_en_ddr4pwr]
set_property PACKAGE_PIN AH23 [get_ports sc0841_interface_en_gtpwr]
set_property PACKAGE_PIN AF24 [get_ports sc0841_interface_en_osc]
set_property PACKAGE_PIN AB20 [get_ports sc0841_interface_pll_scl_io]
set_property PACKAGE_PIN P28 [get_ports sc0841_interface_xio_io]
set_property PACKAGE_PIN AE20 [get_ports sc0841_interface_pg_ddr]
set_property PACKAGE_PIN AH22 [get_ports sc0841_interface_pg_gt]
set_property PACKAGE_PIN AB19 [get_ports sc0841_interface_pll_sda_io]

set_property IOSTANDARD SSTL12_DCI [get_ports sc0841_interface_ddr4_par_44]
set_property IOSTANDARD SSTL12_DCI [get_ports sc0841_interface_ddr4_par_46]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_en_ddr4pwr]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_en_gtpwr]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_en_osc]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pll_scl_io]
set_property IOSTANDARD LVCMOS18 [get_ports sc0841_interface_xio_io]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pg_ddr]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pg_gt]
set_property IOSTANDARD LVCMOS33 [get_ports sc0841_interface_pll_sda_io]

set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_pins -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1}]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

create_clock -period 4.950 -name ddr4_0_clk [get_pins */ddr4_b44/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]
create_clock -period 4.950 -name ddr4_1_clk [get_pins */ddr4_b46/*/u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst/CLKIN1]

# You must provide all the delay numbers
# CCLK delay is 0.1, 6.7 ns min/max for ultra-scale devices; refer Data sheet
# Consider the max delay for worst case analysis
# Max delay constraints are used to instruct the tool to place IP near to STARTUPE3 primitive.
# If needed adjust the delays appropriately
#set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/DO[*] {*STARTUP*_inst/DTS[*]}] 1.000


create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift {6.700 6.700 6.700} [get_pins -hierarchical *USRCCLKO]
set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 2
set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 1
set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 2
set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 1
set_max_delay -datapath_only -from [get_pins -hier {*STARTUP*_inst/DI[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier *STARTUP*_inst/USRCCLKO] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier {*STARTUP*_inst/DO[*]}] 1.000
set_max_delay -datapath_only -from [get_clocks clk_out2_msys_clk_wiz_0_0] -to [get_pins -hier {*STARTUP*_inst/DTS[*]}] 1.000

current_instance msys_i/ddr4_b46/inst
set_property LOC MMCME3_ADV_X0Y2 [get_cells -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst}]
current_instance -quiet
current_instance msys_i/ddr4_b44/inst
set_property LOC MMCME3_ADV_X0Y0 [get_cells -hier -filter {NAME =~ */u_ddr4_infrastructure/gen_mmcme*.u_mmcme_adv_inst}]

current_instance -quiet
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks si5338_clk0_clk_p]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks si5338_clk3_clk_p]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins {msys_i/util_ds_buf_6/U0/USE_BUFG_GT.GEN_BUFG_GT[0].BUFG_GT_U/O}]]
set_false_path -from [get_clocks si5338_clk3_clk_p] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/ddr4_b44/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/ddr4_b46/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins {msys_i/util_ds_buf_5/U0/USE_BUFG_GT.GEN_BUFG_GT[0].BUFG_GT_U/O}]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/ddr4_b44/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]
set_false_path -from [get_clocks -of_objects [get_pins msys_i/ddr4_b46/inst/u_ddr4_infrastructure/gen_mmcme3.u_mmcme_adv_inst/CLKOUT0]] -to [get_clocks -of_objects [get_pins msys_i/clk_wiz_0/inst/mmcme3_adv_inst/CLKOUT0]]

• optional chapter separate

• sections for different apps

----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2021.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

• Modified Files: blconfig.h, bootloader.c
• Changes:
  
  • Add some console outputs and changed bootloader read address.
  • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2021.2 xilisf_v5_11

• Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

fsbl

TE modified 2021.2 FSBL

General:

• Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

• Add Files: te_fsbl_hooks.h/.c (for hooks and board)

• General Changes: 
  
  • Display FSBL Banner and Device ID

Module Specific:

• Add Files: all TE Files start with te_*
  
  • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
  • CPLD access
  • Read CPLD Firmware and SoC Type
  • Configure Marvell PHY

fsbl_flash

TE modified 2021.2 FSBL

General:

• Modified Files: main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2021.2 FSBL

General:

• Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
• Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
• General Changes: 
  
  • Display FSBL Banner and Device Name

Module Specific:

• Add Files: all TE Files start with te_*
  
  • Si5338 Configuration
  • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 2021.2 FSBL

General:

• Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
• General Changes:
  
  • Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

• optional chapter separate

• sections for linux

• Add "No changes." or "Activate: and add List"

#include <configs/microblaze-generic.h>
#include <configs/platform-auto.h>
 
#define CONFIG_SYS_BOOTM_LEN 0xF000000  

/include/ "system-conf.dtsi"
/ {
};

• Add description for other Software, for example SI CLK Builder ...
• SI5338 and SI5345 also Link to:
  • Si5345
  • Si5338

• Note this list must be only updated, if the document is online on public doc!
• It's semi automatically, so do following
  

  • Add new row below first

  • Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

  • Metadata is only used of compatibility of older exports