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| Connector | Signal Schematic Name | Connected to | Notes |
|---|---|---|---|
Pin Header J22 |
| clock generator U17, pin 16 | PS_1V8 VCCIO |
| clock generator U17, pin 18 | ||
SMA Coax J25 |
| clock generator U17, pin 1 | - |
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| Info |
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The PLL clock generator U17 can be reseted resetted by the low active pin 'PLL_RST' connected to SC CPLD U27, bank 4, pin L4. The on-board header J22 provides the possibility to program the clock generator U17 via I²C bus (1.8V reference voltage). |
On-board LEDs
The TEB0911 board is equipped with several LEDs to signal current states and activities.
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Absolute Maximum Ratings
Parameter | Min | Max | Units | Reference Document | Notes | |||
|---|---|---|---|---|---|---|---|---|
VIN supply voltage | -0.3 | 28 | V | TEB0911 Schematic REV03 | - | Storage temperature | °C | - |
Table 63: Module absolute maximum ratings
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
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| VBATT | -0.3 | 6 | V | TPS780180300 data sheet | 1.8V typical output |
| PS GTR receiver input | -0.5 | 1.1 | V | Xilinx DS925 data sheet | - |
| MGT reference clock input | -0.5 | 1.3 | V | Xilinx DS925 data sheet | supplied from FMC connectors |
| GTH transcever input voltage | -0.5 | 1.2 | V | Xilinx DS925 data sheet | - |
| PL I/O input voltage (HP / HD bank) | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet | PL bank VCCO voltages are fixed at 1.8V |
| PS I/O input voltage | -0.5 | VCCO + 0.55 | V | Xilinx DS925 data sheet | see section 'bank voltages' for PS bank VCCO |
| SC CPLD U27 I/O input voltage | -0.5 | 3.75 | V | Lattice MachXO2 familiy data sheet | - |
| PLL clock generator input | -0.85 | 3.8 | V | Si5345/44/42 Rev D Data Sheet | supplied through SMA coax J25 |
Storage temperature | -20 | 60 | °C | TVS Diode Array 82402374 data sheet | - |
Table 63: Module absolute maximum ratings
| Note |
|---|
| Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
| Parameter | Min | Max | Units | Reference Document | Notes |
|---|---|---|---|---|---|
| VIN supply voltage | 22 | 25 | V | Schematic REV03 | 24V nominal |
| VBATT | 2.2 | 5.5 | V | TPS780180300 data sheet | supplied by 3.0V CR1220 battery |
| PL I/O input voltage (HP / HD bank) | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet | PL bank VCCO voltages are fixed at 1.8V |
| PS I/O input voltage | -0.2 | VCCO + 0.2 | V | Xilinx DS925 data sheet | see section 'bank voltages' for PS bank VCCO |
| SC CPLD U27 I/O input voltage | -0.3 | 3.6 | V | Lattice MachXO2 familiy data sheet | - |
| SC CPLD U27 differential I/O input voltage | 0 | 2.605 | V | Lattice MachXO2 familiy data sheet | - |
| PLL clock generator input | -0.2 | 3.0 | V | Si5345/44/42 Rev D Data Sheet | - |
| Operating temperature | 0 | 60 | °C | F455B / Xilinx DS925 data sheet | - |
Table 64: Module recommended operating conditions
| Note |
|---|
| Please check Xilinx datasheet ... |
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Table 64: Module recommended operating conditions
| Note |
|---|
| Please check Xilinx datasheet ... for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
Commercial grade: 0°C to +70°C.
Extended grade: 0°C to +85°C.
Industrial grade: -40°C to +85°C.
Module operating temperature range depends also on customer design and cooling solution. Please contact us for optionsThe TEB0911 board is capable to be operated at an operational temperatur range of 0 °C ... 85 °C without FMC cooling fans M1 ... M6 and NGFF M.2 PCIe socket U2, which limit the temperatur range.
Physical Dimensions
Module size: ... mm × ... mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ... mm.
PCB thickness: ... mm.
Highest part on PCB: approx. ... mm. Please download the step model for exact numbers.
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