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anchor	Figure_8
title	Figure 8: SSD interface

draw.io Diagram

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diagramName	SSD interface diagram formatted
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Connector	Interface	Signal Schematic Name	Connected to	Notes
M.2-NGFF PCIe Socket U2	MGT Lane	B505_TX0_P B505_TX0_N B505_RX0_P B505_RX0_N	PS_MGTRTXP0_505, AB29 PS_MGTRTXN0_505, AB30 PS_MGTRRXP0_505, AB33 PS_MGTRTXN0_505, AB34	Multi gigabit highspeed data lane TX: Output RX: Input
	Clock Input	SSD_RCLK_P SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0	Reference clock signal
	Control Lines	SSD1_LED	SC CPLD U27, bank 2, pin AA13	LED, Output, High active
		SSD1_SLEEP	SC CPLD U27, bank 2, pin AA12	PCIe sleep state, Input, Low active
		SSD1_PERSTN	SC CPLD U27, bank 2, pin AA11	PCIe reset input, Input, Low active
		SSD1_WAKE	SC CPLD U27, bank 2, pin AB11	PCIe Link reactivation, Input, Low active
		SSD1_CLKRQ	connect to GND	PCIe Clock Request, Low active

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