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PHY Pin | Connected to | Notes |
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MDC/MDIO | PS bank 502 MIO76, MIO77 | - |
PHY LED0..2 | SC CPLD U27, bank 4, pin L5, L1, K1 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
PHY_CLK125M | SC CPLD U27, bank 4, pin K2 | 125 MHz Ethernet PHY clock out |
CONFIG | pulled up to PS_1V8 | Configuration of PHY address LSB and VDDO level |
RESETn | SC CPLD U27, bank 4, pin L6 | Active low reset line |
RGMII | PS bank 502 MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
SGMII | - | Serial Gigabit Media Independent Interface |
MDI | RJ45 GbE MagJack J13 | Media Dependent Interface |
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Connector | Signal Schematic Name | Connected to | Notes |
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Fan Connector J2 |
| SC CPLD U27, bank 0, pin E10 | - |
| SC CPLD U27, bank 0, pin D11 | - | |
| SC CPLD U27, bank 0, pin C8 | Controls 12V Load Switch | |
Fan Connector J23 |
| SC CPLD U27, bank 0, pin D9 | - |
| SC CPLD U27, bank 0, pin G12 | - | |
| SC CPLD U27, bank 0, pin B4 | Controls 12V Load Switch | |
Fan Connector J33 |
| SC CPLD U27, bank 0, pin B13 | - |
| SC CPLD U27, bank 0, pin A13 | - | |
| SC CPLD U27, bank 0, pin A12 | Controls 12V Load Switch |
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