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Following table describes the signals and control lines of the Gigabit Ethernet interface of the board:sdfsdfsdf
PHY Pin | Connected to | Notes |
---|---|---|
MDC/MDIO | PS bank 502 MIO76, MIO77 | - |
PHY LED0..2 | SC CPLD U27, bank 4, pin L5, L1, K1 | see schematic for details, forwarded to RJ45 GbE MagJack J7 |
PHY_CLK125M | SC CPLD U27, bank 4, pin K2 | 125 MHz Ethernet PHY clock out |
CONFIG | pulled up to PS_1V8 | Configuration of PHY address LSB and VDDO level |
RESETn | SC CPLD U27, bank 4, pin L6 | Active low reset line |
RGMII | PS bank 502 MIO64 ... MIO75 | Reduced Gigabit Media Independent Interface |
SGMII | - | Serial Gigabit Media Independent Interface |
MDI | RJ45 GbE MagJack J13 | Media Dependent Interface |
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Following table contains a brief description of the control signals of the fan connectors:sdfsdfsdf
Connector | Signal Schematic Name | Connected to | Notes |
---|---|---|---|
Fan Connector J2 |
| SC CPLD U27, bank 0, pin E10 | -PWM signal to fan |
| SC CPLD U27, bank 0, pin D11 | -sense RPM signal of fan | |
| SC CPLD U27, bank 0, pin C8 | Controls 12V Load Switchenable 12V fan supply voltage | |
Fan Connector J23 |
| SC CPLD U27, bank 0, pin D9 | -PWM signal to fan |
| SC CPLD U27, bank 0, pin G12 | -sense RPM signal of fan | |
| SC CPLD U27, bank 0, pin B4 | Controls 12V Load Switchenable 12V fan supply voltage | |
Fan Connector J33 |
| SC CPLD U27, bank 0, pin B13 | -PWM signal to fan |
| SC CPLD U27, bank 0, pin A13 | -sense RPM signal of fan | |
| SC CPLD U27, bank 0, pin A12 | Controls 12V Load Switchenable 12V fan supply voltage |
Table 43: 4-wire PWM fan connectors signals and pins
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