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The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:
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| Connector | Interface | Signal Schematic Name | Connected to | Logic | Notes |
|---|---|---|---|---|---|
SFP+ J9A | MGT Lane |
| MGTHTXP3_129, G31 | TX: Output RX: Input | Multi gigabit highspeed data lane |
| I²C |
| 8-channel I²C-switch U37 | BiDir | 2-wire Serial Interface | |
| Control Lines |
| I²C 8-bit I/O Port-Expander U86 | Output, low active | Full RX bandwidth | |
| Output, low active | Reduced RX bandwidth | |||
| Input, low active | Module present / not present | |||
| Input, high active | Fault / Normal Operation | |||
| SC CPLD U27, bank 2, pin V8 | Input, high active | Loss of receiver signal | ||
| SC CPLD U27, bank 2, pin Y7 | Output, low active | SFP Enabled / Disabled | ||
SFP+ J9B | MGT Lane |
| MGTHTXP2_129, H29 | TX: Output RX: Input | Multi gigabit highspeed |
| I²C |
| 8-channel I²C-switch U37 | Bidir | 2-wire Serial Interface | |
| Control Lines |
| I²C 8-bit I/O Port-Expander U86 | Output, low active | Full RX bandwidth | |
| Output, low active | Reduced RX bandwidth | |||
| Input, low active | Module present / not present | |||
| Input, high active | Fault / Normal Operation | |||
| SC CPLD U27, bank 2, pin W7 | Input, high active | Loss of receiver signal | ||
| SC CPLD U27, bank 2, pin V7 | Output. low active | SFP Enabled / Disabled |
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