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Introduction

This Trenz Electronic teCORE IP provides a RGPIO (Remote GPIO) Interface to talk to external RGPIO Devices over . Convert parallel data bus into 3 wire communicationsignal and back to parallel data bus.

IP can be used as Master communicate with external RGPIO devices with Slave interface or as Slave to communicate with external RGPIO devices with Master interface.

Features

  • Master RGPIO
  • Slave RGPIO
  • GPIO expanderExpander
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teCORE™ IP Facts Table 
Supported Device FamilyUltrasScale+ Zynq, 7 Series Zynq,UltraScale+ Series, UltraScale Series, 7 Series
Supported User InterfacesCustom
Resources
Special FeaturesRGPIO Master and Slave Controller
Provided with Core
Design FilesVHDL Source Code
Constraint FilesNot provided, depends on module PCB
Example DesignNot Provided
Test BenchNot Provided
Simulation ModelNot Provided
Supported S/W DirverNot Provided
Tested Design Flows
Design Entry

Vivado® Design Suite, IP Integrator

SimulationVivado Simulator
SynthesisVivado Synthesis
Tested Hardware Platforms

Support
Provided by Trenz Electronic GmbH

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RGPIO_EXT External Interface

Communication channel between master and slave interface.


Port NameIODescription
RGPIO_M_CLKoutRGPIO Master Clock
RGPIO_M_RXin

RGPIO Master RXD  

RGPIO_M_TXoutRGPIO Master TXD
Port NameIODescription
RGPIO_S_CLKoutRGPIO Slave Clock
RGPIO_S_RXin

RGPIO Slave RXD  

RGPIO_S_TXoutRGPIO Slave TXD


RGPIO_M_USR Interface

Master user interface to communicate with slave device.

Port NameIODescription
RGPIO_M_OUToutData 23bit data output to slave device*
RGPIO_M_INin

Data 23bit data input from slave device*

RGPIO_M_RESERVED_OUTout

Reserved 4bit reserved for future usage

RGPIO_M_RESERVED_INinReserved 4bit reserved for future usage
RGPIO_M_SLAVE_ACTIVATION_CODEoutActivation 4bit activation code from external slave for information only
RGPIO_M_ENABLEinEnable RGPIO communication. High active. Set RGPIO data as valid for Slave. Data will always transmitted, if CLK is available.
RGPIO_M_USRCLKinRGPIO transmission CLK for master and slave
RGPIO_M_RESET_Nin

RGPIO Reset. Low active.

*currently limited to 23 bit to use IP with CPLD implementations of TE Boards. For general usage, this restriction will be removed on future IP update.

RGPIO_

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S_USR Interface

Slave user interface to communicate with master device.

Port NameIODescription
RGPIO_S_OUToutData 23bit  data output to master device*
RGPIO_S_INin

Data 23bit data input from master device*

RGPIO_S_RESERVED_OUToutReserved 4bit reserved for future usage
RGPIO_S_RESERVED_INinReserved 4bit reserved for future usage
RGPIO_S_MASTER_ACTIVATION_CODEoutActivation 4bit activation code from external master for information only
RGPIO_S_ENABLEDoutInterface status. Indicates RGPIO data are valid.

*currently limited to 23 bit to use IP with CPLD implementations of TE Boards. For general usage, this restriction will be removed on future IP update.

Designing with the Core

This chapter includes guidelines and additional information to facilitate designing with the core.

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There is no example Design for this IP core release.


Use Master Slave loopback over RGPIO_EXT interface to test IP Master and Slave Interface together.

Vivado Block Design:

Image Added

VIO HW Manager:

Image Added

Test Bench

There is no test bench for this IP core release.

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Document Change History

DateDocument RevisionIP RevisionAuthorsDescription

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modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.

v1.0

Page info
modified-user
modified-user

  • initial release with Vivado 2017.4

Legal Notices

Include Page
IN:Legal IP Notices TE
IN:Legal IP Notices TE

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