Page History
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- Four SFP+ 10Gb ports
- HPC FMC connector
- Low jitter programmable clock generator
- Intel(Altera) Max10 FPGA 10M08SAU169C8G
- Status LED (green)
Block Diagram
Figure 1: TEF0008-01 block diagram.
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Power Distribution Dependencies
Regulator dependencies and max. current.
Figure 3: Module power distribution diagram.
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Power Rail Name | HPC FMC Connector (J2) | Direction | Notes |
|---|---|---|---|
| 3P3V | D36, D38, D40, C39 | Input | Supply voltage from carrier board. |
| 1.8V | - | Output | Module on-board 1.8V voltage supply (Max 1A). |
3P3VAUX | D32 | Input | Supply voltage from carrier board. |
VADJ | H40, G39, F40, E39 | Input | Supply voltage from carrier board. |
| 12V | C35, C37 | Input | Not used supply voltage from carrier board. |
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Overview
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