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anchor	Figure_1
title	Figure 1: TEB0911-03 block diagram

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Main Components

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anchor	Figure_3
title	Figure 3: General overview of the FMC connectors

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HTML
<!-- MGT lanes should be listed separately, as they are more specific than just general I/Os. -->

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anchor	Figure_4
title	Figure 4: XMOD header J24 and J35

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Signal Assignment of XMOD header J24 and J35

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anchor	Figure_5
title	Figure 5: Gigabit Ethernet interface

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Following table describes the signals and control lines of the Gigabit Ethernet interface of the board:

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anchor	Figure_6
title	Figure 6: USB3 interface

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The 4-port USB3 hub is connected to the Zynq MPSoC's PS GTR bank, the USB2 PHY is connected to the PS MIO bank 502:

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anchor	Figure_7
title	Figure 7: SFP+ interface

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Connector	Interface	Signal Schematic Name	Connected to	Logic	Notes
SFP+ J9A	MGT Lane	B129_TX3_P B129_TX3_N B129_RX3_P B129_RX3_N	MGTHTXP3_129, G31 MGTHTXN3_129, G32 MGTHRXP3_129, F33 MGTHRXN3_129, F34	TX: Output RX: Input	Multi gigabit highspeed data lane
	I²C	SFP0_SDA SFP0_SCL	8-channel I²C-switch U37	BiDir	2-wire Serial Interface
	Control Lines	SFP0_RS0	I²C 8-bit I/O Port-Expander U86	Output, low active	Full RX bandwidth
		SFP0_RS1		Output, low active	Reduced RX bandwidth
		SFP0_M-DEF0		Input, low active	Module present / not present
		SFP0_TX_FAULT		Input, high active	Fault / Normal Operation
		SFP0_LOS	SC CPLD U27, bank 2, pin V8	Input, high active	Loss of receiver signal
		SFP0_TX_DIS	SC CPLD U27, bank 2, pin Y7	Output, low active	SFP Enabled / Disabled
SFP+ J9B	MGT Lane	B129_TX2_P B129_TX2_N B129_RX2_P B129_RX2_N	MGTHTXP2_129, H29 MGTHTXN2_129, H30 MGTHRXP2_129, H33 MGTHRXN2_129, H34	TX: Output RX: Input	Multi gigabit highspeed data lane
	I²C	SFP1_SDA SFP1_SCL	8-channel I²C-switch U37	Bidir	2-wire Serial Interface
	Control Lines	SFP1_RS0	I²C 8-bit I/O Port-Expander U86	Output, low active	Full RX bandwidth
		SFP1_RS1		Output, low active	Reduced RX bandwidth
		SFP1_M-DEF0		Input, low active	Module present / not present
		SFP1_TX_FAULT		Input, high active	Fault / Normal Operation
		SFP1_LOS	SC CPLD U27, bank 2, pin W7	Input, high active	Loss of receiver signal
		SFP1_TX_DIS	SC CPLD U27, bank 2, pin V7	Output. low active	SFP Enabled / Disabled

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anchor	Figure_8
title	Figure 8: SSD interface

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Connector	Interface	Signal Schematic Name	Connected to	Notes
M.2-NGFF PCIe Socket U2	MGT Lane	B505_TX0_P B505_TX0_N B505_RX0_P B505_RX0_N	PS_MGTRTXP0_505, AB29 PS_MGTRTXN0_505, AB30 PS_MGTRRXP0_505, AB33 PS_MGTRTXN0_505, AB34	Multi gigabit highspeed data lane TX: Output RX: Input
	Clock Input	SSD_RCLK_P SSD_RCLK_N	Quad programmable PLL clock generator U12, CLK0	Reference clock signal
	Control Lines	SSD1_LED	SC CPLD U27, bank 2, pin AA13	LED, Output, High active
		SSD1_SLEEP	SC CPLD U27, bank 2, pin AA12	PCIe sleep state, Input, Low active
		SSD1_PERSTN	SC CPLD U27, bank 2, pin AA11	PCIe reset input, Input, Low active
		SSD1_WAKE	SC CPLD U27, bank 2, pin AB11	PCIe Link reactivation, Input, Low active
		SSD1_CLKRQ	connect to GND	PCIe Clock Request, Low active

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anchor	Figure_9
title	Figure 9: DisplayPort interface

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Follwowing table contains a brief description of the MGT lanes and control and status signals of the DisplayPort interface:

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anchor	Figure_10
title	Figure 10: DDR4 memory interface

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Following table gives an overview about the I/O signals of the DDR4 SDRAM memory interface:

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anchor	Figure_11
title	Figure 11: CAN interface

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The CAN interface of external devices can be connected via D-SUB 9-pin male connector J3 or to the 6-pin male header J15:

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anchor	Figure_12
title	Figure 12: SD Card interface

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The SD Card socket have following signal and pin assignment:

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anchor	Figure_13
title	Figure 13: 4-wire PWM FAN connectors

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Following table contains a brief description of the control signals of the fan connectors:

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anchor	Figure_14
title	Figure 14: PLL clock interface

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Connector

Signal Schematic Name

Connected to

Notes

Pin Header

J22

PLL_SCL

clock generator U17, pin 16

PS_1V8 VCCIO

PLL_SDA

clock generator U17, pin 18

SMA Coax

J25

CLK_PLL_IN

clock generator U17, pin 1

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anchor	Figure_15
title	Figure 15: I/O's connecting Zynq MPSoC and SC CPLD

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For detailed information about the current function of the MIO-pin in conjunction with the SC CPLD, the internal signal assignment and implemented logic, refer to the Wiki reference page of the SC CPLD firmware of this board or into the bitstream file of the SC CPLD.

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anchor	Figure_16
title	Figure 16: Power distribution diagram

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Power distribution to the MPSoC PS and PL units:

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anchor	Figure_17
title	Figure 17: Power distribution diagram continued

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Info
Note: The DC-DC converter U91 LTM4630EY has an integrated temperature diode for device temperature monitoring. The analog signal 'TEMP_CORE_DC' on pin J6 of the converter is routed to the dedicated differential analog interface (XADC) of the Zynq MPSoC, pin U18 (V_P), pin V17 (V_N) is connected to analog GND.

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anchor	Figure_18
title	Figure 18: Power-On sequence diagram

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Power Rails

Peripheral Designator	VCC / VCCIO Schematic Name	Voltage	Direction	Pins	Notes
J12	DP_TX_PWR	3.3V	Out	Pin 20	Display-Port Connector
J9A	SFP_SSD	3.3V	Out	Pin T15, T16	SFP+ 2x1 Connector
J9B	SFP_SSD	3.3V	Out	Pin L15, L16	SFP+ 2x1 Connector
J13A	VBUS1	5.0V	Out	Pin U1	USB3 Ports
J13B	VBUS2	5.0V	Out	Pin U10	USB3 Ports
J11	-	3.3V	Out	Pin 4	MicroSD Card Socket
B1	PSBATT	3.0V	In	Pin +	Battery Holder CR1220
U2	SSD1_3V3_1	3.3V	Out	Pin 2, 4	SSD PCIe connector
	SSD1_3V3_2	3.3V	Out	Pin 70, 72, 74
	SSD1_3V3_3	3.3V	Out	Pin 12, 14, 16, 18
U3	DDR_1V2	1.2V	Out	Pin 111, 112, 117, 118, 123, 124, 129, 130, 135, 136, 141, 142, 147, 148, 153, 154, 159, 160, 163	DDR4 SO-DIMM socket
U3	VPP_SPD	2.5V	Out	Pin 255, 257, 259	DDR4 SO-DIMM socket

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Trenz Electronic Documentation

Versions Compared

Old Version 154

New Version 155

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Main Components

Power Rails