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Table 1: Initial delivery state of programmable devices on the module.
Boot Process
For the boot process prior to powering up the board settings must be done via DIP-Switch S3-3 and S3-4. Four boot modes can be selected:
| S3-3 (SC_SW1) | S3-4 (SC_SW2) | MIO Location | Description | Notes |
|---|---|---|---|---|
| OFF | OFF | MIO[43:38] | SD1 Boot Mode (SD-Card on J11) | Supports SD 2.0. |
| OFF | ON | MIO[29:26] | PJTAG0 | PS JTAG connection 0 option. |
| ON | OFF | MIO[12:0] | QSPI32 | 32-bit addressing, configured with dual on-board QSPI Flash Memory. |
| ON | ON | - | JTAG | Dedicated PS interface. |
Table 2: Available boot modes of the on-board Zynq MPSoC
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The TEB0911 Ultrarack+ offers 6 FMC (FPGA Mezzanine Card) connectors which provides as an ANSI/VITA 57.1 standard a modular interface to the MPSoCs FPGA and exposes numerous of its I/O pins and MGT Lanes lanes for use by other mezzanine modules and expansion cards.
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