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Overview

Refer to https://wiki.trenz-electronic.de/display/PD/TE0808+TRM for the current online version of this manual and other available documentation.

The Trenz Electronic TE0808 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+ MPSoC, up to 8 GBytes of DDR4 SDRAM via 64-bit wide data bus, max. 512 MByte Flash memory for configuration and operation, 20 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/Os are provided via rugged high-speed stacking connections. All this in a compact 5.2 x 7.6 cm form factor, at the competitive price.

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

• MPSoC: ZYNQ UltraScale+ ZU9EG 900 pin package
• Memory
  - 64-Bit DDR4, 8 GByte maximum
  - Dual SPI boot Flash in parallel, 512 MByte maximum
• User I/Os
  - 65 x PS MIOs, 48 x PL HD GPIOs,  156 x PL HP GPIOs (3 banks)
  - Serial transceivers: 4 x GTR + 16 x GTH
  - Transceiver clocks inputs and outputs
  - PLL clock generator inputs and outputs
• Si5345 - 10 output PLL
• All power supplies on board, single 3.3V power source required
  - 14 on-board DC-DC regulators and 13 LDOs
  - LP, FP, PL separately controlled power domains
• Support for all boot modes (except NAND) and scenarios
• Support for any combination of PS connected peripherals
• Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
• B2B connectors: 4 x 160 pin

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Table 2: B2B connector pin-outs of available PL and PS banks of the TE0808-04 SoM. 

All MIO banks are powered from on-module DC-DC power rail. All PL I/O Banks have separate VCCO pins in the B2B connectors, valid VCCO should be supplied from the baseboard.

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Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq MPSoC PS QSPI0 interface via PS MIO bank 500, pins MIO0 ... MIO5 and MIO7 ... MIO12.

Table 7: PS MIO pin assignment of the Quad SPI Flash memory ICs.

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Table 11: Programmable PLL clock generator input/output. 

The Si5345A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5345A data sheet.

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