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<!-- For the detailed function of the pins and signals, the internal signal assignment and implemented logic, look to the Wiki reference page SC CPLD of this module or into the bitstream file of the SC CPLD. Add link to the Wiki reference page of the SC CPLD, if available. --> |
I2C Interface
OnDespite the EEPROM U4 all other on-board I2C devices are connected to the MAX10 FPGA for level shift and I²C MUX. Addresses for on-board devices are listed in the table below:. The EEPROM is accessed via the FMC connector.
| I2C Device | I2C Address | Notes |
|---|---|---|
| J4, SFP+ | 1100001 / 1100000 | Conventional SFP Memory / Enhanced Feature Set Memory, Device select via MAX10 FPGA implementation. |
| J5, SFP+ | 1100001 / 1100000 | Conventional SFP Memory / Enhanced Feature Set Memory, Device select via MAX10 FPGA implementation. |
| J6, SFP+ | 1100001 / 1100000 | Conventional SFP Memory / Enhanced Feature Set Memory, Device select via MAX10 FPGA implementation. |
| J7, SFP+ | 1100001 / 1100000 | Conventional SFP Memory / Enhanced Feature Set Memory, Device select via MAX10 FPGA implementation. |
| U2, Si5345A | 1101001 | Level shifted via MAX10 FPGA, Device select via MAX10 FPGA implementation. |
| U4, EEPROM | 10100xx | Last digits determined by carrier board via HPC FMC (C34 GA0, C35 GA1). |
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