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For more information refer to the TE0820 CPLD - BootMode section. 

Signals, Interfaces and Pins

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Table 7: System Controller CPLD special purpose pins.

See also TE0820-REV01_REV02 CPLD.

Page break

Default PS MIO Mapping

PS MIOFunctionB2B PinConnected toPS MIOFunctionB2B PinConnected to
0SPI0-U7-B2, CLK40..45--Not connected
1SPI0-U7-D2, DO/IO1
46SDJM1-17B2B, SD_DAT3
2SPI0-U7-C4, WP/IO2
47SD

JM1-19

B2B, SD_DAT2
3SPI0-U7-D4, HOLD/IO348SD

JM1-21

B2B, SD_DAT1
4SPI0-U7-D3, DI/IO0 49SDJM1-23B2B, SD_DAT0
5SPI0- U7-C2, CS50SDJM1-25B2B, SD_CMD
6N/A-Not connected51SDJM1-27B2B, SD_CLK
7SPI1-U17-C2, CS52USB_PHY-U18-31, OTG-DIR
8SPI1-U17-D3, DI/IO053USB_PHY-U18-31, OTG-DIR
9SPI1-U17-D2, DO/IO154USB_PHY-U18-5, OTG-DATA2
10SPI1-U17-C4, WP/IO255USB_PHY-U18-2, OTG-NXT
11SPI1-U17-D4, HOLD/IO356USB_PHY-U18-3, OTG-DATA0
12SPI1-U17-B2, CLK57USB_PHY-U18-4, OTG-DATA1
13..20eMMC-U6, MMC-D0..D758USB_PHY-U18-29, OTG-STP
21eMMC-U6, MMC-CMD59USB_PHY-U18-6, OTG-DATA3
22eMMC-U6, MMC-CLKR60USB_PHY-U18-7, OTG-DATA4
23eMMC-U6, MMC-RST61USB_PHY-U18-9, OTG-DATA5
24ETH-U8, ETH-RST62USB_PHY-U18-10, OTG-DATA6
25USB_PHY-U18, OTG-RST

63

USB_PHY-U18-13, OTG-DATA7
26MIOJM1-95B2B, as PJTAG MIO possible64ETH-U8-53, ETH-TXCK
27MIOJM1-93B2B, as PJTAG MIO possible65..66ETH-U8-50..51, ETH-TXD0..1
28MIOJM1-99B2B, as PJTAG MIO possible67..68ETH-U8-54..55, ETH-TXD2..3
29MIOJM1-99B2B, as PJTAG MIO possible69ETH-U8-56, ETH-TXCTL
30MIOJM1-92B2B (UART RX)70ETH-U8-46, ETH-RXCK
31MIOJM1-85B2B (UART TX)71..72ETH-U8-44..45, ETH-RXD0..1
32MIOJM1-91B2B73..74ETH-U8-47..48, ETH-RXD2..3
33MIOJM1-87B2B75ETH-U8-43, ETH-RXCTL
34..37--Not connected76ETH-U8-7, ETH-MDC
38I2C-U10-12, SCL77ETH-U8-8, ETH-MDIO
39I2C-U10-19, SDA----

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

John Hartfiel
  • Rework chapter currently available products
  • add PJTAG note to MIOtable
2018-03-12v.54
  • Correction Power Rail Section
2017-11-20v.51John Hartfiel
  • Correction Default MIO Configuration Table
2017-11-10v.50John Hartfiel
  • Replace B2B connector section
2017-10-18v.49John Hartfiel
  • add eMMC section
2017-09-25v.48John Hartfiel
  • Correction in the "Board to Board (B2B) I/Os" section
  • Update in the "Variants Currently In Production" section
2017-09-18v.47John Hartfiel
  • Update PS MIO table
2017-08-30v.46Jan Kumann
  • MGT lanes section added.

2017-08-24

v.36

John Hartfiel
  • Correction in the  "Key Features" section.
2017-08-21v.34John Hartfiel
  • "Initial delivery state" section updated.
2017-08-21v.33Jan Kumann
  • HW revision 02 block diagram added.
  • Power distribution and power-on sequence diagram added.
  • System Controller CPLD and DDR4 SDRAM sections added.
  • TRM update to the template revision 1.6
  • Weight section removed.
  • Few minor corrections.


2017-08-18

v.7

John Hartfiel
  • Style changes
  • Updated "Boot Mode", "HW Revision History", "Variants Currently In Production" sections
  • Correction of MIO SD Pin-out, System Controller chapter
  • Update and new sub-sections on "On Board Peripherals and Interfaces" sections

2017-08-07

v.5

Jan Kumann

Initial version.

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