Page History

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Main Components

Photo shows similar TE0841-01

1. Xilinx Zynq UltraScale+ MPSoC, U1
2. 1.8V, 512 Mbit QSPI flash memory, U7
3. 1.8V, 512 Mbit QSPI flash memory, U17
4. 8 Gbit (512 x 16) DDR4 SDRAM, U2
5. 8 Gbit (512 x 16) DDR4 SDRAM, U3
6. Marvell Alaska 88E1512 integrated 10/100/1000 Mbps energy efficient ethernet transceiver, U8
7. 6A PowerSoC DC-DC converter (PL_VCCINT, 0.85V), U5
8. B2B connector Samtec Razor Beam™ LSHM-150, JM1
9. B2B connector Samtec Razor Beam™ LSHM-150, JM2
10. B2B connector Samtec Razor Beam™ LSHM-130, JM3
11. 4 GByte eMMC memory, U6
12. Lattice Semiconductor MachXO2 System Controller CPLD, U21
13. I²C programmable, any  frequency , any output  quad clock generator, U10
14. Highly integrated full featured hi-speed USB 2.0 ULPItransceiver, U18

Initial Delivery State

Table 1: Initial delivery state of programmable devices on the module

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Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.

Table 2: Boot mode pin description

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Zynq MPSoC's I/O banks signals connected to the B2B connectors:

Table 3: General overview of board to board I/O signals

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The Xilinx Zynq UltraScale+ device used on the TE0820 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

Table 4: MGT lanes

There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Table 5: MGT reference clock sources

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JTAG access to the Xilinx Zynq-7000 is provided through B2B connector JM2.

Table 6: JTAG interface signals

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Special purpose pins are connected to System Controller CPLD and have following default configuration:

Table 7: System Controller CPLD special purpose pins.

See also TE0820-REV01_REV02 CPLD

Default PS MIO Mapping

Table 8: TE0820-02 PS MIO mapping

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On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.

Ethernet PHY connection

Table 9: General overview of the Gigabit Ethernet PHY signals

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USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 25.000000 MHz oscillator (U15).

USB PHY connection

Table 10: General overview of the USB PHY signals.

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On-board I²C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I²C1 by default. Addresses for on-board I²C slave devices are listed in the table below:

Table 11: Address table of the I²C bus slave devices.

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Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGA.

Table 12: General overview of the on-board quad clock generator I/O signals

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The module has following reference clock signals provided by on-board oscillators and external source from carrier board:

Table 13: Reference clock signals

On-board LEDs

Table 14: On-board LEDs

Power and Power-on Sequence

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Power supply with minimum current capability of 3A for system startup is recommended.

Power Consumption

Table 15: Power consumption

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See also Xilinx datasheet DS892 DS925 for additional information. User should also check related base board documentation when intending base board design for TE0841 TE0820 module.

Power-On Sequence

The TE0820 SoM meets the recommended criteria to power up the Xilinx Zynq chip properly by keeping a specific sequence of enabling the on-board DC-DC converters dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages.

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Figure 4: TE0820-03 power-on sequence diagram.

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See Xilinx datasheet DS925 for additional information. User should also check related carrier board documentation when choosing carrier board design for TE0715 module.

Power Rails

Table 16: TE0820-02 power rails

Bank Voltages

Table 17: TE0820-02 I/O bank voltages

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Variants Currently In Production

Technical Specifications

Absolute Maximum Ratings

Table 18: Module absolute maximum ratings

Recommended Operating Conditions

Table 19: Recommended operating conditions

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Hardware Revision History

Table 20: Hardware revision history table.

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Table 21: Document change history

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