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XMOD-Header J35 is designated to program the System Controller CPLD U27 via USB interface, the 4 GPIO/UART pins (XMOD1_A/B/E/G) of this header are also routed to the System Controller CPLD U27.
To program the System Controller CPLD, the JTAG interface of this devices have to be activated by DIP-switch S3-2. J35 JTAG is used for FMC JTAG, is JTAGENB is low (see CPLD Firmware).
When using XMOD FTDI JTAG Adapter TE0790, the adapter-board's VCC and VCCIO on both headers J24 and J35 will be sourced by the on-board supply voltages. Set the XMOD DIP-switch with the setting:
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| Note |
|---|
Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out without 'L') to program the Xilinx Zynq devices. The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download. |
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| Si5338A Pin | Signal Schematic Name | Connected to | Clock Direction | Note |
|---|---|---|---|---|
IN1 |
| U17, pin 54 | Input | Differential reference clock input from PLL clock generator U17 |
| IN2 |
| U17, pin 53 | Input | |
IN3 | - | U85, pin 3 | Input | 25.000000 MHz oscillator, Si8008AI |
IN4 | - | GND | Input | LSB (pin 'IN4') of the default I²C-adress 0x70 not set |
IN5 | - | Not connected | Input | Not used |
| IN6 | - | GND | Input | Not used |
CLK0A |
| U2, pin 55 | Output | NGFF M.2 PCIe socket (Key M), |
| CLK0B |
| U2, pin 53 | Output | |
| CLK1A |
| U1, pin U27 | Output | PS GTR Bank 505 Lane 2, dedicated for DisplayPort, |
| CLK1B |
| U1, pin U28 | Output | |
| CLK2A |
| U1, pin W27 | Output | PS GTR Bank 505 Lane 1, dedicated for USB3 interface |
| CLK2B |
| U1, pin W28 | Output | |
| CLK3A |
| U1, pin AA27 | Output | PS GTR Bank 505 Lane 0, dedicated for SSD interface |
| CLK3B |
| U1, pin AA28 | Output |
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