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Main Components

1. Xilinx Zynq-7000 SoC, U1
2. 4Gbit DDR3L SDRAM, U19
3. 4Gbit DDR3L SDRAM, U10
4. 4Gbit DDR3L SDRAM, U8
5. 4Gbit DDR3L SDRAM, U9
6. 4Gbit DDR3L SDRAM, U14
7. 4Gbit DDR3L SDRAM, U12
8. SI5338A programmable quad PLL clock generator, U2
9. SiTime SiT8008 25.000000 MHz oscillator, U3
10. Lattice Semiconductor MachXO2 4000HC CPLD, U32
11. Microchip 128Kbit I²C EEPROM, U26
12. Microchip 2Kbit I²C MAC EEPROM, U22
13. TPS780180300 LDO @1.8V backup battery voltage, U21
14. TCA9406DCUR I²C voltage level shifter, U25
15. Intersil ISL12020MIRZ Real Time Clock, U17
16. Microchip USB3320C USB PHY transceiver, U4
17. SiTime SiT8008 52.000000 MHz oscillator, U7
18. 74AVCH4T245 voltage level tranlator, U30
19. TPS74801RGW LDO @1.5V, U23
20. 32 MByte QSPI Flash memory, U38
21. LT quad 4A PowerSoC DC-DC converter (@1.0V), U13
22. LT quad 4A PowerSoC DC-DC converter (@3.3V, @1,8V, @1.2V_MGT, @1.0V_MGT), U16
23. TPS74801RGW LDO @1.5V_PL, U20
24. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J2
25. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J3
26. Samtec ASP-122952-01 160-pin stacking strip (2 rows a 80 positions), J1
27. Micron Technology 4 GByte eMMC, U28
28. Marvell Alaska 88E1512 Gigabit Ethernet PHY, U18
29. Texas Instruments TXS02612RTWR SDIO Port Expander, U29
30. SiTime SiT8008 25.000000 MHz oscillator, U11
31. DSC1123CI2 Low-Jitter Precision LVDS Oscillator, U31
32. SiTime SiT8008 33.333333 MHz oscillator, U33
33. TPS799 LDO @1.8V_MGT, U5
34. TPS799 LDO @VCCAUX_IO (1.8V), U35

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Table 1: Initial delivery state of programmable devices on the module

Boot Process

4 6 of the 7 boot mode strapping pins (MIO2 ... MIO8) of the Xilinx Zynq-7000 SoC device are hardware programmed on the board, 3 1 of them are is set be by the SC CPLD firmware. They The boot strapping pins are evaluated by the Zynq device soon after the 'PS_POR' signal is deasserted to begin the boot process (see section "Boot Mode Pin Settings" of Xilinx manual UG585).

The TE0783 board is programmed in boot mode is selected by the pin 'CPLD_GPIO3' of the SC CPLD firmware to boot initially , which is connected to B2B pin J2-16 to either from the on-board QSPI Flash memory U38 or SD IO interface. See section Bootmode in the TE0783 SC CPLD reference Wiki page.

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Table 2: General overview Table 2: General overview of board to board I/O signals

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There are 2 clock sources for the GTX transceivers. MGT_CLK1, MGT_CLK2, MGT_CLK4 and MGT_CLK4 CLK7 are connected directly to B2B connector J3 and J1, so the clock can be provided by the carrier board. Clocks MGT_CLK0, MGT_CLK3, MGT_CLK5 and MGT_CLK6 are provided by the on-board clock generator (U2). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.

Table 4: MGT reference clock sources

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Table 7: System Controller CPLD special purpose pins.

See also TE0783 CPLD reference Wiki page.

Default PS MIO Mapping

Table 7: System Controller CPLD special purpose pins.

See also TE0783 CPLD reference Wiki page.

Default PS MIO Mapping

Table 8: Zynq PS MIO mapping

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The TE0783 is equipped with two one Marvell Alaska 88E1512 Gigabit Ethernet PHYs (U18 (ETH1) and U20 (ETH2)). The transceiver PHY of ETH1 is connected to the Zynq PS Ethernet GEM0. The I/O Voltage is fixed at 1.8V for HSTL signaling. The reference clock input for both of the PHYs is supplied from an on board 25MHz oscillator (U11), the 125MHz output clock of both PHYs are connected to Zynq's PL bank 35.

ETH1 GbE PHY connection:

Table 9: General overview of the Gigabit Ethernet1 PHY signals

USB Interface

The TE0783 is equipped with one USB PHY USB3320 from Microchip (U4). The ULPI interface of the USB PHY is connected to the Zynq PS USB0. The I/O Voltage is fixed at 1.8V.

The reference clock input of the PHY is supplied from an on board 52MHz oscillator (U7).

USB2 ETH2 PHY connection:

Table 10: General overview of the Gigabit Ethernet2 PHY signals

USB Interface

The TE0783 is equipped with two USB PHY's USB3320 from Microchip (U4 (USB0) and U8 (USB1)). The ULPI interface of USB0 is connected to the Zynq PS USB0, ULPI interface of USB1 to Zynq PS USB1. The I/O Voltage is fixed at 1.8V.

The reference clock input of both PHY's is supplied from an on board 52MHz oscillator (U7).

USB0 PHY connection:

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Table 10: General overview of the Gigabit Ethernet2 PHY signals

I2C Interface

The on-board I²C components are connected to PS MIO bank 500 pins MIO10 ('MIO10_SCL') and MIO11 ('MIO11_SDA').

I²C addresses for on-board components:

Table 11: Address table of the I²C bus slave devices

Table 11: General overview of the Gigabit Ethernet2 PHY signals

USB1 PHY connection:

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Table 12: General overview of the Gigabit Ethernet2 PHY signals

I2C Interface

The on-board I²C components are connected to bank 35 pins L15 (I2C_SDA) and L14 (I2C_SCL).

I²C addresses for on-board components:

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Table 13: Address table of the I²C bus slave devices

Pin Definitions

Pins with names ending with _VRN and _VRP are connected to Zynq PL HP bank special purpose pins VRN/VRP and can be routed to DCI calibration resistors on the baseboard. Otherwise they are usable as general purpose I/Os.

Bank 35 has 100 ohm DCI calibration resistors installed, it is also possible to "borrow" the DCI calibration from bank 35 for banks 34 and 33. For more detailed information about the DCI check Xilinx documentation.

On-board Peripherals

System Controller CPLD

The System Controller CPLD (U14U32) is provided by Lattice Semiconductor LCMXO2-1200HC 4000HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0783 CPLD reference Wiki page.

eMMC Flash Memory

eMMC Flash memory device (U15U28) is connected to the Zynq PS MIO bank 500 501 pins MIO10MIO46..MIO15MIO51. eMMC chips MTFC4GMVEA-4M IT (Flash NAND-IC 2x 16 Gbit) is used with 4 GByte of memory density.

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DDR3 Memory

By default TE0783-01 module has two 16-bit wide IM (Intelligent Memory) IM4G16D3FABG-125I DDR3L SDRAM (DDR3-1600 Speedgrade) chips arranged into 32-bit wide memory bus providing total of 1 GBytes of on-board RAM.

Quad SPI Flash Memory

Two One quad SPI compatible serial bus flash memory for Flash memory (U38) for FPGA configuration file storage is provided by Spansion S25FL256SAGBHI20 with 256 Mbit (32 MByte) memory density. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

Gigabit Ethernet

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PHY

On-board Gigabit Ethernet PHYs PHY (U18, U20) are is provided by Marvell Alaska 88E1512. The Ethernet PHYsPHY's RGMII interfaces are interface is connected to the Zynq's PS MIO bank 501 and to PL bank 9. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of both PHYs the PHY is supplied from an on-board 25.000000 MHz oscillator (U11).

High-speed USB2 ULPI

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PHY

Hi-speed USB ULPI PHYs PHY (U4. U8) are is provided with USB3320 from Microchip. The ULPI interfaces are interface is connected to the Zynq PS USB0 and USB1 via MIO28..51, bank 501 (see also section USB interface). The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.000000 MHz oscillator (U7).

MAC Address

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EEPROM

Two A Microchip 24AA025E48 serial EEPROMs EEPROM (U22, U24) contain globally unique 48-bit node address, which are compatible with EUI-48(TM) specification. The devices are device is organized as two blocks of 128 x 8 Kbit memory. One of the blocks stores the 48-bit node address and is write protected, the other block is available for application use. The MAC address EEPROMS areaccessible EEPROM is accessible over I²C bus (see also section I²C interface).

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