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Pin NameDirectionFunctionDefault Configuration
EXT_IO1 ... EXT_IO40in / outuser GPIO on B2Bsee current CPLD firmware
BOOTMODEininsignal forwarded to MIO9 and currently used as UART RX line
CONFIGXinoutsignal forwarded to MIO8 and currently used as UART TX line
NRST_INinnRESET inputexternal Board Reset
M_TDOoutCPLD JTAG interface



-
M_TDIin
M_TCKin
M_TMSin
JTAGENBinenable JTAGpull high for programming SC CPLD firmware
ETH1_RESEToutreset GbE PHY U18see current SC CPLD firmware
OTG-RSToutreset USB2 PHYs
U4 and U8
see current SC CPLD firmware
DONEinZynq control signalPL configuration completed
PROG_BoutPL configuration reset signal
PS_PORoutPS power-on reset
BM2/MIO4out

Bootmode Pin: SD or QSPI

MIO14inuser MIO pins

currently used as UART interface
MIO15out
LED2outRed LED D1 status signalsee current CPLD firmware
CPLD_GPIO0 ... CPLD_GPIO3in / outuser GPIO on B2BCPLD_GPIO3 used for Boot Modesee current CPLD firmware
FPGA_CPLD1 ... FPGA_CPLD4in /outuser GPIO to FPGA bank 9see current SC CPLD firmware
EN_1VoutPower controlenable signal DCDC U13 '1V'
PG_ALLin

power good signal all voltages powered up properly

→ Green LED D2 lights up.

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Scroll Title
anchorFigure_45
titleFigure 45: TE0783-01 Power-on Sequence DiagramVoltage Monitor Circuit
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draw.io Diagram
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viewerToolbartrue
fitWindowfalse
diagramNameTE0783-01 Voltage Monitor Circuit
simpleViewerfalse
width
diagramWidth641
revision1

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Power Rails

Power Rail Name on B2B ConnectorJ1 PinsJ2 PinsJ3 PinsDirectionNotes
VIN-165, 166, 167, 168-Inputexternal power supply voltage
C3.3V-147, 148-InputNormally leave unconnected
3.3V-

111, 112, 123, 124, 135 136

169, 170, 171, 172

-Outputinternal 3.3V voltage level
1.8V169, 170, 171, 172--Outputinternal 1.8V voltage level
EXT_IO_VCC99, 100--InputSC CPLD bank 1, 2 and 4 voltage
VCCIO_10--99, 100Inputhigh range I/O bank voltage
VCCIO_11--159, 160Inputhigh range I/O bank voltage
VCCIO_12-159, 160-Inputhigh range I/O bank voltage
VCCIO_13-99, 100-Inputhigh range I/O bank voltage
VBAT_IN--124Inputbackup battery voltage

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anchorFigure_56
titleFigure 56: Module physical dimensions drawing

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Scroll Title
anchorFigure_67
titleFigure 67: Module hardware revision number

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