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Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC

Large number of configurable I/Os are provided via rugged HPC FMC connector

Dual ARM Cortex-A9 MPCore
- 1 GByte RAM (32-Bit wide DDR3)
- 32 MByte QSPI Flash memory
- 2 x Hi-Speed USB2 ULPI transceiver PHY
- 2 x Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
- 4 GByte eMMC (optional up to 64 GByte)
2 x MAC-address EEPROMs
Optional 2x 64 MByte HyperFLASH or 2x 8 MByte HyperRAM (max 2x 32 MByte HyperRAM)
Temperature compensated RTC (real-time clock)
Si5338A programmable quad PLL clock generator for GTX transceiver clocks
Plug-on module with 3 x 160-pin high-speed strips
- 16 GTX high-performance transceiver
- 2x GT transceiver clock inputs
- 254 FPGA I/O's (125 LVDS pairs)
- 16 GTX high-performance transceiver
- 2x MGT transceiver clock inputs
- 254 FPGA HR I/O's (125 LVDS pairs)
Si5338A programmable quad PLL clock generator for GTX transceiver clocks
On-board high-efficiency switch-mode DC-DC On-board high-efficiency switch-mode DC-DC converters
System management
eFUSE bit-stream encryption
AES bit-stream encryption
Evenly-spread supply pins for good signal integrity
User LED
PCI Express 2.0 x8 card with maximum throughput of 4 GB/s
FMC High Pin Count (HPC) connector
8 FPGA MGT lanes available on PCIe interface
DDR3 SO-DIMM SDRAM socket
256-Mbit (32-MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
- FPGA
- JTAG port (SPI indirect, bus width x4)
External clock input via SMA coaxial connector
28 GTH transceivers, each with up to 13.1 Gbit/s data transmission rate
FPGA configuration through:
- JTAG connector
- Quad SPI Flash memory
Programmable quad clock generator
TI LMK04828B ultra low-noise JESD204B compliant clock jitter cleaner
On-board high-efficiency DC-DC converters
Up to 202 FPGA I/O pins available on FMC connector (up to 101 LVDS pairs possible)
System management and power sequencing
AES bit-stream encryption
eFUSE bit-stream encryption
Xilinx Kintex UltraScale FPGA (XCKU035 or XCKU040)
2 banks of 1024 MByte DDR4 SDRAM, 32bit wide memory interface
512 Mbit (64 MByte) QSPI Flash
3 x Samtec Razor Beam LSHM B2B, 260 terminals total
- 60 x HR I/Os
- 84 x HP I/Os
- 8 x GTH transceiver lanes (TX/RX)
- 2 x MGT external clock inputs
Clocking
- Si5338 - 4 output PLLs, GT and PL clocks
- 200 MHz LVDS oscillator
All power supplies on-board, single power source operation
Evenly spread supply pins for optimized signal integrity
Size: 40 x 50 mm
3 mm mounting holes for skyline heat spreader
Rugged for industrial applications

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title	Figure 1: TEF1001-02 block diagram

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I/O signals connected to the SoCs I/O bank and B2B FMC connector J2:

FPGA Bank	Type	I/O Signal Count	Bank VCCO Voltage	Notes
6412	HR	48 IO's, 24 LVDS pairs	B64FMC_VCCOVADJ	Supplied by the carrier board	Bank voltage supplied by DC-DC converter U7
1365	HR	8 34 IO's	3.3V	On-module power supply
65	HR	4 IO's	3.3V	On-module power supply
, 17 LVDS pairs	FMC_VADJ
15	HR	34	66	HP	16 IO's, 8 17 LVDS pairs	B66FMC_VCCO	Supplied by the carrier board	67	HP	VADJ
16	HR	44 48 IO's, 24 22 LVDS pairs	B67VIO_B_VCCOFMC	Supplied by the carrier board
67	HP	2 IO's	B67_VCCO	Supplied by the carrier board
68	HP	18 IO's, 9 LVDS pairs	B68_VCCO	Supplied by the carrier boardBank voltage supplied by FMC connector J2

Table 2: General overview of FPGA's PL I/O signals connected to the FMC connector

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MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, two signals each or four signals total per one MGT lane. The MGT lanes are connected to the FMC connector and to the PCIe x8 connector. Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:

4116

Lane	Bank	Type	Signal Name	PCIe Connector Pin	FPGA Pin
0	115	GTX	MGT_RX0PER3_PMGT_RX0 PER3_N MGT_TX0PET3_PMGT_TX0 PET3_N	JM3J1-8A29JM3 J1-10A30 JM3J1-7B27JM3 J1-9B28	MGTHRXP0MGTXTXP0_225115, Y2P2MGTHRXN0 MGTXTXN0_225115, Y1P1MGTHTXP0 MGTXRXP0_225115, AA4R4MGTHTXN0 MGTXRXN0_225115, AA3R3
1	115	GTX	MGT_RX1PER2_PMGT_RX1 PER2_N MGTPET2_TX1_PMGT_TX1 PET2_N	JM3J1-14A25JM3 J1-16A26 JM3J1-13B23JM3 J1-15B24	MGTHRXP1MGTXTXP1_225115, V2M2MGTHRXN1 MGTXTXN1_225115, V1M1MGTHTXP1 MGTXRXP1_225115, W4N4MGTHTXN1 MGTXRXN1_225115, W3N3
2	115	GTX	MGTPER1_RX2_PMGT_RX2 PER1_N MGT_TX2PET1_PMGT PET1_TX2_N	JM3J1-20A21JM3 J1-22A22 JM3J1-19B19JM3 J1-21B20	MGTHRXP2MGTXTXP2_225115, T2K2MGTHRXN2 MGTXTXN2_225115, T1K1MGTHTXP2 MGTXRXP2_225115, U4L4MGTHTXN2 MGTXRXN2_225115, U3L3
3	115	GTX	MGT_RX3PER0_PMGT PER0_RX3_N MGTPET0_TX3_PMGT PET0_TX3_N	JM3J1-26A16JM3 J1-28A17 JM3J1-25B14JM3 J1-27B15	MGTHRXP3MGTXTXP3_225115, P2H2MGTHRXN3 MGTXTXN3_225115, P1H1MGTHTXP3 MGTXRXP3_225115, R4J4MGTHTXN3 MGTXRXN3_225115, R3J3
Lane	Bank	Type	Signal Name	FMC Connector Pin	FPGA Pin
0	116	GTX	DP3_M2C	GTX	MGT_RX4_PMGT DP3_RX4M2C_N MGTDP3_TX4C2M_PMGT DP3_TX4C2M_N	JM1J2-12A10JM1 J2-10A11 JM1J2-6A30JM1 J2-4A31	MGTHRXP0MGTXRXP0_224116, AH2G4MGTHRXN0 MGTXRXN0_224116, AH1G3MGTHTXP0 MGTXTXP0_224116, AG4F2MGTHTXN0 MGTXTXN0_224116, AG3F1
51	116	GTX	MGTDP2_RX5M2C_PMGT DP2_RX5M2C_N MGTDP2_TX5C2M_PMGT DP2_TX5C2M_N	JM1J2-24A6JM1 J2-22A7 JM1J2-18A26JM1 J2-16A27	MGTHRXP1MGTXRXP1_224116, AF2E4MGTHRXN1 MGTXRXN1_224116, AF1E3MGTHTXP1 MGTXTXP1_224116, AF6D2MGTHTXN1 MGTXTXN1_224116, AF5D1
62	116	GTX	MGTDP1_RX6M2C_PMGT DP1_RX6M2C_N MGTDP1_TX6C2M_PMGT DP1_TX6C2M_N	JM1J2-27A2JM1 J2-25A3 JM1J2-19A22JM1 J2-17A23	MGTHRXP2MGTXRXP2_224116, AD2C4MGTHRXN2 MGTXRXN2_224116, AD1C3MGTHTXP2 MGTXTXP2_224116, AE4B2MGTHTXN2 MGTXTXN2_224116, AE3B1
73	116	GTX	MGTDP0_RX7M2C_PMGT DP0_RX7M2C_N MGTDP0_TX7C2M_PMGT DP0_TX7C2M_N	JM3J2-2C6JM3 J2-4C7 JM3J2-1C2JM3 J2-3C3	MGTHRXP3MGTXRXP3_224116, AB2B6MGTHRXN3 MGTXRXN3_224116, AB1B5MGTHTXP3 MGTXTXP3_224116, AC4A4MGTHTXN3 MGTXTXN3_224116, AC3A3

Table 3: FPGA to B2B connectors routed MGT lanes overview

Below are listed MGT banks reference clock sources:

Clock signal	Bank	Source

LaneFPGA BankTypeSignal Name

	FPGA Pin

FMC Pin0117GTH

Notes
MGTCLK_5338

DP0_M2C

_P

DP0_M2C_N
DP0_C2M_P
DP0_C2M_N

MGTHRXP0_117, N4
MGTHRXN0_117, N3
MGTHTXP0_117, M2
MGTHTXN0_117, M1

J2A-C6
J2A-C7
J2A-C2
J2A-C3

1

117

GTH

DP1_M2C_P
DP1_M2C_N
DP1_C2M_P
DP1_C2M_N

MGTHRXP1_117, L4
MGTHRXN1_117, L3
MGTHTXP1_117, K2
MGTHTXN1_117, K1

J2A-A2
J2A-A3
J2A-A22
J2A-A23

2

117

GTH

DP2_M2C_P
DP2_M2C_N
DP2_C2M_P
DP2_C2M_N

MGTHRXP2_117, K6
MGTHRXN2_117, K5
MGTHTXP2_117, H2
MGTHTXN2_117, H1

J2A-A6
J2A-A7
J2A-A26
J2A-A27

3

117

GTH

DP3_M2C_P
DP3_M2C_N
DP3_C2M_P
DP3_C2M_N

MGTHRXP3_117, J4
MGTHRXN3_117, J3
MGTHTXP3_117, F2
MGTHTXN3_117, F1

J2A-A10
J2A-A11
J2A-A30
J2A-A31

4

118

GTH

DP4_M2C_P
DP4_M2C_N
DP4_C2M_P
DP4_C2M_N

MGTHRXP0_118, G4
MGTHRXN0_118, G3
MGTHTXP0_118, D2
MGTHTXN0_118, D1

J2A-A14
J2A-A15
J2A-A34
J2A-A35

Clock Signal	MGT Bank	Source	FPGA Pin	Notes
MGTCLK_5338_P	115	U13, CLK1A	MGTREFCLK0P_115, AB6	On-board Si5338A.
MGTCLK_5338_N	115	U13, CLK1B	MGTREFCLK0N_115, AB5	On-board Si5338A.
PCIE_CLK_P	115	J1-A13, REFCLK+	MGTREFCLK1P_115, AD6	External clock from PCIe slot.
PCIE_CLK_N	115	J1-A14, REFCLK-	MGTREFCLK1N_115, AD6	External clock from PCIe slot.
CLK_SYNTH_DCLKOUT4_P	116	U9, DCLKout4	MGTREFCLK0P_116, T6	On-board LMK04828B.
CLK_SYNTH_DCLKOUT4_N	116	U9, DCLKout4*	MGTREFCLK0N_116, T6	On-board LMK04828B.
GBTCLK0_M2C_P	117	J2-D4	MGTREFCLK0P_117, M6	External clock from FMC connector.
GBTCLK0_M2C_N	117	J2-D5	MGTREFCLK0N_117, M5	External clock from FMC connector.
GBTCLK1_M2C_P	117	J2-B20	MGTREFCLK1P_117, P6	External clock from FMC connector.
GBTCLK1_M2C_N	117	J2-B21	MGTREFCLK1N_117, P5	External clock from FMC connector.
CLK_SYNTH_SDCLKOUT7_P	118	U9, DCLKout7	MGTREFCLK0P_118,F6	On-board LMK04828B.
CLK_SYNTH_SDCLKOUT7_N	118	U9, DCLKout7*	MGTREFCLK0N_118,F5	On-board LMK04828B.
MGTCLK2_5338_P	118	U13, CLK3A	MGTREFCLK1P_118, H6	On-board Si5338A.
MGTCLK2_5338_N	118	U13, CLK3B	MGTREFCLK1N_118, H5	On-board Si5338A.

115	U13, CLK1A	MGTREFCLK0P_115, H6	Supplied by on-board Si5338A
115	MGTCLK_5338_N	U13, CLK1B	Supplied by on-board Si5338A	MGTREFCLK0N_115, H5
PCIE_CLK_P	115	J1-A13, REFCLK+	MGTREFCLK1P_115, K6	External clock from PCIe slot
PCIE_CLK_N	115	J1-A14, REFCLK-	MGTREFCLK1N_115, K6	External clock from PCIe slot
GBTCLK0_M2C_P	116	J2-D4	MGTREFCLK0P_116, D6	External clock from FMC connector
GBTCLK0_M2C_N	116	J2-D5	MGTREFCLK0N_116, D5	External clock from FMC connector
GBTCLK1_M2C_P	116	J2-B20	MGTREFCLK1P_116, F6	External clock from FMC connector
GBTCLK1_M2C_N	116	J2-B21	MGTREFCLK1N_116, F5	External clock from FMC connector

JTAG Interface	Signal Schematic Name	JTAG Connector Pin	Connected to
CPLD JTAG VCCIO: 3.3V Connector: J8	CPLD_JTAG_TMS	J8-1	SC CPLD, bank 0, pin 90
	CPLD_JTAG_TDI	J8-2	SC CPLD, bank 0, pin 94
	CPLD_JTAG_TDO	J8-3	SC CPLD, bank 0, pin 95
	CPLD_JTAG_TCK	J8-4	SC CPLD, bank 0, pin 91

FPGA JTAG VCCIO: 1.8V Connector: J9	FPGA_JTAG_TMS	J9-4	FPGA, bank 0, pin N9
	FPGA_JTAG_TCK	J9-6	FPGA, bank 0, pin M8
	FPGA_JTAG_TDO	J9-8	FPGA, bank 0, pin N8
	FPGA_JTAG_TDI	J9-10	FPGA, bank 0, pin L8

FMC JTAG VCCIO: 3.3V Connector: J2	FMC_TRST	J2-D34	SC CPLD, bank 2, pin 36
	FMC_TCK	J2-D29	SC CPLD, bank 2, pin 27
	FMC_TMS	J2-D33	SC CPLD, bank 2, pin 28
	FMC_TDI	J2-D30	SC CPLD, bank 2, pin 31
	FMC_TDO	J2-D31	SC CPLD, bank 2, pin 32

Pin Name	SC CPLD Direction	Function	Default Configuration
JTAG_EN	Input	JTAG select	Low for normal operation
nRST_SC0	Input	Reset	Low active board reset input
SC1	-	-	not currently used ('BOOTMODE' in default B2B pin out')
SC2	Input / Output	-	Power good signal ('PGOOD' in default B2B pin out)
SC3	Input	-	Power enable pin ('EN1' in default B2B pin out)
SC4	-	-	not currently used ('NOSEQ' in default B2B pin out')
F_TCK	Output	JTAG signals between SC CPLD and FPGA	B2B JTAG signals are forwarded to the FPGA through SC CPLD.
F_TMS	Output
F_TDI	Output
F_TDO	Input
TCK	Input	JTAG signals between SC CPLD and B2B connector	Program FPGA or SC CPLD depending on pin JTAGMODE.
TMS	Input
TDI	Input
TDO	Output
PROG_B	Output	FPGA configuration	PL configuration reset signal.
DONE	Input	FPGA configuration done	PL configuration completed.
PUDC_B	Output	Pull up during configuration	PL I/O's are 3-stated until configuration of the FPGA completes.
INIT_B	Input	Initialization done	Low active FPGA initialization pin or configuration error signal.
EN_PL	Input	Enable PL Power DC-DC converters	Set to contant logical high.
CPLD_IO	Output	user I/O	Connected to FPGA Bank 45, pin P28.

CPLD Functionality	Interface	Designated CPLD Pins	Connected to	Notes
I²C interface between on-board peripherals and FPGA	I²C	FPGA_IIC_SDA, pin 24 FPGA_IIC_SCL, pin 25 FPGA_IIC_OE, pin 19	FPGA bank 16, pin V29 FPGA bank 16, pin W29 FPGA bank 16, pin W26	VCCIO: 1V8, all with pull-up to 1V8. Following devices and connectors are linked to the FPGA_IIC I²C interface: DC-DC converter U3 and U4 (LT LTM4676) Programmable quad clock generator U13 FMC connector J2 PCIe connector J1 Note: FPGA_IIC_OE must kept high for I²C operation. For I²C slave device addresses refer to the component datasheets.
User I/Os External LVDS pairs	10 I/Os 5 x LVDS pairs	EX0_P ... EX4_P EX0_N ... EX4_N	IDC header J7	Can also be used for single-ended signaling.
User I/Os Internal LVDS pairs	13 I/Os 6 x LVDS pairs	FEX0_P ... FEX5_P FEX0_N ... FEX5_N FEX_DIR (single-ended I/O)	FPGA bank 18	VCCIO: 1V8 Can also be used for single-ended signaling. FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK). Internal signal assignment: FEX_DIR <= FMC_PRSNT_M2C_L
FPGA programming control and state	2 I/Os	DONE, pin 7 PROGRAM_B, pin 8	FPGA bank 0, pin V8 FPGA bank 0, pin U8	VCCIO: 1V8
I²C interface to programmable quad clock generator	I²C	PLL_SCL, pin 14 PLL_SDA, pin 15	U13, pin 12 U13, pin 19	VCCIO: 1V8 Only PLL_SDA has 1V8 pull-up.
Fan PWM control J4	2 I/Os	F1SENSE, pin 99 F1PWM, pin 98	J4-3 (active low) J4-4	Internal signal assignment: FEX_5_P <= F1SENSE FEX_5_N => F1PWM
Button S2	1 I/O	BUTTON, pin 77	Switch S2	Functionality depends on CPLD firmware, activating pin PROGRAM_B (active low) and LED1 in standard configuration.
LED1	1 I/O	LED1, pin 76	LED D1 (green)	Fast blinking, when FPGA is not programmed. Internal signal assignment: LED1 <= Button S2 or FEX0_P
PCIe control line RESET_B	1 I/O	PCIE_RSTB, pin 37	J1-A11	Internal signal assignment: FEX_4_N <= PCIE_RSTB
Control interface to clock synthesizer U9 (TI LMK04828B)	SPI (3 I/Os), 4 I/Os	CLK_SYNTH_SDIO, pin 75 CLK_SYNTH_SCK, pin 74 CLK_SYNTH_RESET, pin 54 CLK_SYNTH_CS, pin 53 CLK_SYNTH_SYNC, pin 52 LMK_STAT0, pin 62 LMK_STAT1, pin 63	U9, pin 20 U9, pin 19 U9, pin 5 U9, pin 18 U9, pin 6 U9, pin 31 U9, pin 48	Pull up to 3V3PCI. Internal signal assignment: LMK_SCK <= FEX_1_P LMK_SDIO <= FEX_1_N LMK_CS <= FEX_3_P LMK_SYNC <= EX_3_N LMK_RESET <= FEX_4_P FEX_2_P => LMK_SDIO (FEX_2_N must be 0) LMK_STAT0 and LMK_STAT1 signals are not used.
Control Interface to DC-DC converters U3 and U4 (both LTM4676)	I²C (2 I/Os), 2 I/Os	LTM_SCL, pin 67 LTM_SDA, pin 66 LTM1_ALERT, pin 65 LTM2_ALERT, pin 64	U4, pin E6 and U3, pin E6 U4, pin D6 and U3, pin D6 U4, pin E5 U3, pin E5	3V3 pull-ups. LTM I²C interface is also accessible trough header J10. LTM1_ALERT and LTM2_ALERT signals are not used.
Power-on sequence and monitoring	6 I/Os	EN_1V8, pin 58 PG_1V8, pin 59 EN_FMC_VADJ, pin 60 PG_FMC_VADJ, pin 61 EN_3V3, pin 51 PG_3V3, pin 57	U20, pin 27 U20, pin 28 U7, pin 27 U7, pin 28 U15, pin 27 U15, pin 28	Sequence of the supply voltages depend on the System Controller CPLD firmware. EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up. PG signals will not be evaluated.

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Versions Compared

Old Version 10

New Version 11

Key

JTAG Interface

JTAG Interface

System Controller CPLD I/O Pins

System Controller CPLD I/O Pins

Lane	FPGA Bank	Type	Signal Name	FPGA Pin	FMC Pin
5	118	GTH	DP5_M2C_P DP5_M2C_N DP5_C2M_P DP5_C2M_N	MGTHRXP1_118, E4 MGTHRXN1_118, E3 MGTHTXP1_118, C4 MGTHTXN1_118, C3	J2A-A18 J2A-A19 J2A-A38 J2A-A39
6	118	GTH	DP6_M2C_P DP6_M2C_N DP6_C2M_P DP6_C2M_N	MGTHRXP2_118, D6 MGTHRXN2_118, D5 MGTHTXP2_118, B2 MGTHTXN2_118, B1	J2A-B16 J2A-B17 J2A-B36 J2A-B37
7	118	GTH	DP7_M2C_P DP7_M2C_N DP7_C2M_P DP7_C2M_N	MGTHRXP3_118, B6 MGTHRXN3_118, B5 MGTHTXP3_118, A4 MGTHTXN3_118, A3	J2A-B12 J2A-B13 J2A-B32 J2A-B33
8	116	GTH	DP8_M2C_P DP8_M2C_N DP8_C2M_P DP8_C2M_N	MGTHRXP2_116, U4 MGTHRXN2_116, U3 MGTHTXP2_116, T2 MGTHTXN2_116, T1	J2A-B8 J2A-B9 J2A-B28 J2A-B29
9	116	GTH	DP9_M2C_P DP9_M2C_N DP9_C2M_P DP9_C2M_N	MGTHRXP3_116, R4 MGTHRXN3_116, R3 MGTHTXP3_116, P2 MGTHTXN3_116, P1	J2A-B4 J2A-B5 J2A-B24 J2A-B25