Page History

• FPGA_IIC_SDA, pin 24
• FPGA_IIC_SCL, pin 25
• FPGA_IIC_OE, pin 19

• FPGA bank 16, pin V29
• FPGA bank 16, pin W29
• FPGA bank 16, pin W26

VCCIO: 1V8, all with pull-up to 1V8.

Following devices and connectors are linked to the FPGA_IIC I²C interface:

• DC-DC converter U3 and U4 (LT LTM4676)
• Programmable quad clock generator U13
• FMC connector J2
• PCIe connector J1

Note: FPGA_IIC_OE must kept high for I²C operation.

For I²C slave device addresses refer to the component datasheets.

User I/Os

External LVDS pairs

10 I/Os

5 x LVDS pairs

• EX0_P ... EX4_P
• EX0_N ... EX4_N

• IDC header J7

Can also be used for single-ended signaling.

User I/Os

Internal LVDS pairs

13 I/Os

6 x LVDS pairs

• FEX0_P ... FEX5_P
• FEX0_N ... FEX5_N
• FEX_DIR (single-ended I/O)

• FPGA bank 18

VCCIO: 1V8

Can also be used for single-ended signaling.

FPGA bank 18 has also reference clock input from FMC connector (CLK2, CLK3) and clock synthesizer U9 (FCLK).

Internal signal assignment:

FEX_DIR <= FMC_PRSNT_M2C_L

• DONE, pin 7
• PROGRAM_B, pin 8

• FPGA bank 0, pin V8
• FPGA bank 0, pin U8

• PLL_SCL, pin 14
• PLL_SDA, pin 15

• U13, pin 12
• U13, pin 19

VCCIO: 1V8

Only PLL_SDA has 1V8 pull-up.

• F1SENSE, pin 99
• F1PWM, pin 98

• J4-3 (active low)
• J4-4

Internal signal assignment:

• FEX_5_P <= F1SENSE
• FEX_5_N => F1PWM

• BUTTON, pin 77

• Switch S2

• LED1, pin 76

• LED D1 (green)

Fast blinking, when FPGA is not programmed.

Internal signal assignment:

• LED1 <= Button S2 or FEX0_P

PCIe control line RESET_B

• PCIE_RSTB, pin 37

• J1-A11

Internal signal assignment:

• FEX_4_N <= PCIE_RSTB

Control interface to clock synthesizer U9 (TI LMK04828B)

SPI (3 I/Os),

4 I/Os

• CLK_SYNTH_SDIO, pin 75
• CLK_SYNTH_SCK, pin 74
• CLK_SYNTH_RESET, pin 54
• CLK_SYNTH_CS, pin 53
• CLK_SYNTH_SYNC, pin 52
• LMK_STAT0, pin 62
• LMK_STAT1, pin 63

• U9, pin 20
• U9, pin 19
• U9, pin 5
• U9, pin 18
• U9, pin 6
• U9, pin 31
• U9, pin 48

Pull up to 3V3PCI.

• Internal signal assignment:
• LMK_SCK <= FEX_1_P
• LMK_SDIO <= FEX_1_N
• LMK_CS <= FEX_3_P
• LMK_SYNC <= EX_3_N
• LMK_RESET <= FEX_4_P
• FEX_2_P => LMK_SDIO (FEX_2_N must be 0)
• LMK_STAT0 and LMK_STAT1 signals are not used.

I²C (2 I/Os),

2 I/Os

• LTM_SCL, pin 67
• LTM_SDA, pin 66
• LTM1_ALERT, pin 65
• LTM2_ALERT, pin 64

• U4, pin E6 and U3, pin E6
• U4, pin D6 and U3, pin D6
• U4, pin E5
• U3, pin E5

3V3 pull-ups.

LTM I²C interface is also accessible trough header J10.

LTM1_ALERT and LTM2_ALERT signals are not used.

• EN_1V8, pin 58
• PG_1V8, pin 59
• EN_FMC_VADJ, pin 60
• PG_FMC_VADJ, pin 61
• EN_3V3, pin 51
• PG_3V3, pin 57

• U20, pin 27
• U20, pin 28
• U7, pin 27
• U7, pin 28
• U15, pin 27
• U15, pin 28

Sequence of the supply voltages depend on the System Controller CPLD firmware.

EN_1V8, EN_3V3 and EN_FMC_VADJ will be set simultaneously at start-up.

PG signals will not be evaluated.