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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

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Key Features

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Revision History

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Release Notes and Know Issues

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Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

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Additional Sources

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Prebuilt

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<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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File

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File-Extension

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Description

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Debian SD-Image

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*.img

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Debian Image for SD-Card

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MCS-File

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*.mcs

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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

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MMI-File

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*.mmi

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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

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SREC-File

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*.srec

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Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

• TE0??? "Test Board" Reference Design

Design Flow

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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Vivado/SDK/SDSoC
• Vivado Projects
•  Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

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1. Use TE Template from /os/petalinux
   Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.

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1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
   Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"

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1. 1. vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis 
      Projects contains 3 FSBL template: zynq_fsbl (FSBL modified for DDR Less application → use for Boot.bin), zynq_fsbl_app (FSBL modified for DDR Less application and with demo app included → create Boot with this FSBL and Bitstream only), zynq_fsbl_flash(FSBL modified for Flash programming →FSBL which must be selected separately to program Flash)

      Info
      TE0722  is without DDR, so special FSBL (sources on reference designs) is needed, see also: DDR less ZYNQ Design

      
      

Launch

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Note: Programming and Startup procedure

Basic Information, see TE0722 Getting Started

Programming

Note
Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection

   3. Select create and open delivery binary folder

      Info
      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated

      
      

QSPI-Boot mode

Set Board to JTAG Bootmode. Short pins of J4.

Option for Boot.bin on QSPI Flash

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

3. Type on Vivado TCL Console:

   Code Block
   language py theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash)
   TE::pr_program_flash -swapp zynq_fsbl_app

   
   

SD-Boot mode

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot only. See also Xilinx AR#66846

JTAG

The JTAG Bootmode can be set on the newer pcb revisions, REV04+ (short both pins of J4)

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)

3. Power On PCB

   Expand
   title boot process
   1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream 3. FSBL starts application (included into the FSBL Code)

   
   

Standalone Application

Note: UART over J2 is used, this is only available, if PL part is configured with correct UART connection.

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200

   2. select COM Port
      

      Info
      Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)

      
      

2. Output:
   1. Default output appears only a few seconds. Reboot device: force ResN pin to GND for short time, location see: TE0722 Getting Started
      SD card FAT32 Format should be inserted for SD access.
      Image Added
      
      

Vivado HW Manager

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Note: Add picture of HW Manager add notes for the signal either groups or topics, for example: Control: add controllable IOs with short notes.. Monitoring: add short notes for signals which will be monitored only SI5338 CLKs: Set radix from VIO signals to unsigned integer. Note: Frequency Counter is inaccurate and displayed unit is Hz expected CLK Frequ:...

Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)

• Control:
  • Enable/Disable RGB LED Counter (default on)
  • Enable/Disable different colors (default all off) - set to '1' to enable RGB LED
    

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System Design - Vivado

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Block Design

draw.io Diagram
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PS Interfaces

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Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Type Note DDR Disabled! QSPI MIO SD MIO UART0 EMIO I2C1 MIO GPIO MIO SWDT0 EMIO TTC0..1 EMIO

Constraints

Basic module constraints

Code Block
language ruby title _i_bitgen_common.xdc
# # Common BITGEN related settings for TE0722 # set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design]

Design specific constraints

Code Block
language ruby title _i_uart_j2xmod.xdc
set_property PACKAGE_PIN K15 [get_ports UART_0_txd] set_property PACKAGE_PIN L13 [get_ports UART_0_rxd] set_property IOSTANDARD LVCMOS33 [get_ports UART_0_*]

Code Block
language ruby title _i_io.xdc
#RGB LED #R set_property PACKAGE_PIN J15 [get_ports {RGB_LED[0]}] #G set_property PACKAGE_PIN L14 [get_ports {RGB_LED[1]}] #B set_property PACKAGE_PIN K12 [get_ports {RGB_LED[2]}] set_property IOSTANDARD LVCMOS33 [get_ports {RGB_LED[*]}]

Software Design - Vitis

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For Vitis project creation, follow instructions from:

Vitis

Application

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SDSoC (only tested on Win OS)

1. Generate Platform Project or use prebuilt from download
2. ...

Launch

Programming

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
4. Copy image.ub on SD-Card
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
5. Insert SD-Card

SD

1. Copy image.ub and Boot.bin on SD-Card.
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Set Boot Mode to SD-Boot.
   • Depends on Carrier, see carrier TRM.
3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

1. Prepare HW like described on section Programming
2. Connect UART USB (most cases same as JTAG)
3. Select SD Card as Boot Mode
   Note: See TRM of the Carrier, which is used.
4. Power On PCB
   Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root

Vivado HW Manager

SI5338_CLK0 Counter: 

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System Design - Vivado

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Block Design

PS Interfaces

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

Source location: \sw_lib\sw_apps

zynqmp_fsbl

Xilinx default FSBL

zynqmp_fsbl_flash

TE modified 2018.2 FSBL

Changes:

• Set FSBL Boot Mode to JTAG
• Disable Memory initialisation

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

No changes.

U-Boot

No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
};

Kernel

No changes.

Rootfs

No changes.

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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No additional software is needed.

SI5338

Download  ClockBuilder Desktop for SI5338

1. Install and start ClockBuilder
2. Select SI5338
3. Options → Open register map file
   Note: File location <design name>/misc/Si5338/RegisterMap.txt
4. Modify settings
5. Options → save C code header files
6. Replace Header files from FSBL template with generated file

SDSoC Design

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• SDSoC Projects

Description currently not available.

SDSoC Platform

SDSoC Demo Examples

SDSoC platform includes 21 demo projects demonstrating optimization techniques for Standalone and Linux targets with HW acceleration or in SW for fast compilation and debug. These projects have been downloaded and installed into the SDSoC platform from https://github.com/Xilinx/SDSoC_Examples

• array_partition
• burst_rw
• custom_data_type
• data_access_random
• dependence_inter
• direct_connect
• dma_sg
• dma_simple
• full_array_2d
• hello_vadd
• lmem_2rw
• loop_fusion
• loop_perfect
• loop_pipeline
• loop_reorder
• row_array_2d
• shift_register
• systolic_array
• sys_port
• wide_memory_rw
• window_array_2d

There are 3 larger Linux demo projects demonstrating video processing with data I/O from file to file. Source code of these projects have been installed into this platform from the Xilinx SDSoC 2016.4 release:

• file_io_manr_sobel
• file_io_optical
• file_io_sbm

These larger Linux demo projects demonstrate video processing with data I/O from file to file. Source code of these projects have been installed into this platform from demos present in the Xilinx SDSoC 2016.4 release.

Compilation steps in the SDSoC 2017.1 is identical to above described examples. File I/O demos support only the Linux target.

These three files use as an input larger video files. These files have to be present on the SD card as an input. Algorithms write output file to the SD card. These files can be visualized by YUV Player Deluxe and other players. To reduce size of the project, the video data files are not included.

Video input files can be found in the Xilinx SDSoC 2016.4 distribution:

• <xilinx install path>\SDx\2016.4\samples\file_io_manr_sobel\input.yuv
• <xilinx install path>\SDx\2016.4\samples\file_io_optical\route85_1920x1080.yuv
• <xilinx install path>\SDx\2016.4\samples\file_io_sbm\desk_1280x720.yuv

Array partition

This example shows how to use array partitioning to improve performance of a hardware function.

Key Concepts:

•  Hardware Function Optimization
•  Array Partitioning

Keywords:

•  #pragma HLS ARRAY_PARTITION
•  complete

Burst rw

This is a simple vector increment example which demonstrates usage of AXI4-master interface for burst read and write.

Key Concepts:

•  Burst Access

Custom data type

This is a simple example of RGB to HSV conversion to demonstrate Custom Data Type usage in hardware accelerator. Xilinx HLS compiler supports custom data type to operate within the hardware function and also it acts as a memory interface between PL to DDR.

Key Concepts:

•  Custom Data Type

Keywords:

•  struct
•  packed
•  aligned

Data access random

This is a simple example of matrix multiplication (Row x Col) to demonstrate random data access pattern.

Key Concepts:

•  Data Access Random

Keywords:

•  #pragma HLS PIPELINE
•  #pragma SDS access_pattern(a:RANDOM, b:RANDOM)
•  #pragma SDS data copy

Dependence inter

This is a simple example to demonstrate inter dependence attribute using vertical convolution example. Using inter dependence attribute user can provide additional dependency details to compiler which allow compiler to perform unrolling/pipelining to get better performance.

Key Concepts:

•  Inter Dependence

Keywords:

•  DEPENDENCE
•  inter

Direct connect

This is a simple example of matrix multiplication with matrix addition (Out = (A x B) + C) to demonstrate direct connection which helps to achieve increasing in system parallelism and concurrency.

Key Concepts:

•  Direct Connection
•  Multiple Accelerators

Keywords:

•  #pragma SDS data access_pattern(in1:SEQUENTIAL, in2:SEQUENTIAL, out:SEQUENTIAL)

Dma sg

This example demonstrates how to use Scatter-Gather DMAs for data transfer to/from hardware accelerator.

Key Concepts:

•  Scatter Gather DMA

Keywords:

•  #pragma SDS access_parttern(a:SEQUENTIAL)
•  #pragma SDS data_mover(a:AXIDMA_SG)
•  #pragma SDS data copy

Dma simple

This example demonstrates how to insert Simple DMAs for data transfer between User program and hardware accelerator.

Key Concepts:

• Simple DMA

Keywords:

• #pragma SDS access_parttern(a:SEQUENTIAL)
• #pragma SDS data_mover(a:AXIDMA_SIMPLE)
• #pragma SDS data copy

Full array 2d

This is a simple example of accessing full data from 2D array.

Key Concepts:

•  2D data array access

Hello vadd

...

This is a basic hello world kind of example which demonstrates how to achieve vector addition using hardware function.

Key Concepts:

•  - Loop Pipelining

Keywords:

•  - #pragma HLS PIPELINE

Lmem 2rw

This is a simple example of vector addition to demonstrate how to utilize both ports of Local Memory.

Key Concepts:

•  Hardware Function Optimization
•  2port BRAM Utilization
•  Two read/write Local Memory

Keywords:

•  #pragma HLS UNROLL FACTOR=2

Loop fusion

This example will demonstrate how to fuse two loops into one to improve the performance of a C/C++ hardware function.

Key Concepts:

•  Hardware Function Optimization
•  Loop Fusion
•  Loop Pipelining

Keywords:

•  #pragma HLS PIPELINE

Loop perfect

This nearest neighbor example is to demonstrate how to achieve better performance using perfect loop.

Key Concepts:

• Loop perfect

Keywords:

• #pragma HLS PIPELINE
• #pragma HLS ARRAY_PARTITION

Loop pipeline

This example demonstrates how loop pipelining can be used to improve the performance of a hardware function.

Key Concepts:

• Loop Pipelining

Keywords:

• #pragma HLS PIPELINE

Loop reorder

This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering.

Key Concepts:

•  Hardware Function Optimization
•  Loop Reorder to Improve II

Keywords:

•  #pragma HLS PIPELINE
•  #pragma HLS ARRAY_PARTITION

Row array 2d

This is a simple example of accessing each row of data from 2D array.

Key Concepts:

• Row of 2D data array access

Keywords:

• hls::stream

Shift register

This example demonstrates how to shift values in each clock cycle.

Key Concepts:

• Hardware Function Optimization
• Shift Register
• FIR

Keywords:

• #pragma HLS ARRAY_PARTITION

Systolic array

This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note : Systolic array based algorithm design is well suited for FPGA.

Key Concepts:

• Systolic Array

Keywords:

• #pragma HLS PIPELINE
• #pragma HLS ARRAY_PARTITION

Sys port

This is a simple example which demonstrates sys_port usage.

Key Concepts:

• sys_port
• memory interface
• memory non-caching

Keywords:

• #pragma SDS data sys_port
• #pragms HLS PIPELINE
• sds_alloc_non_cacheable

Wide memory rw

This is a simple example of vector addition to demonstrate Wide Memory Access using structure data type of 128bit wide. Based on input argument type, sds++ compiler will figure out the memory interface datawidth of hardware accelerator.

Key Concepts:

• wide memory access
• burst read and write
• custom datatype

Keywords:

• struct

Window array 2d

This is a simple example of accessing window of data from 2D array.

Key Concepts:

• Window of 2D data array access

Keywords:

• #pragma HLS DATAFLOW
• #pragma HLS PIPELINE
• #pragma HLS stream

File IO Video Processing

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing includes Motion Adaptive Noise Reduction (MANR) followed by a Sobel filter for edge detection. You can run it by supplying a 1080p YUV422 file as input with limiting number of frames to a maximum of 20 frames.

Key Concepts:

• Video processing from file to file
• Direct connection of HW accelerated blocks

Select the "File IO Video Processing" template an compile for Linux target as project te22. Copy result to root of SD card. Copy also the input file input.yuv (82 944 000 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by comman ./te22.elf ./input.yuv 20 3 ./output.yuv

The output.yuv file contains 20 frames of 1080p vido in YUV422 format with computed edges. Copy output.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Dense Optical Flow

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs LK Dense Optical Flow over two Full HD frames video file. You can run it by supplying a 1080p YUV422 file route85_1920x1080.yuv as input.

Key Concept:s

• Video processing from file to file
• Direct connection of HW accelerated blocks
• Top down methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.

Select the "File IO Dense Optical Flow" template an compile for Linux target as project te23. Copy result to root of SD card. Copy also the input file route85_1920x1080.yuv (8 294 400 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te23.elf

The OptFlow_1920x1080.yuv file is generated and stored on the SD card. It contains one 1080p frame in YUV422 format with computed dense optical flow vectors. Copy OptFlow_1920x1080.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Stereo Block Matching

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs Stereo Block Matching to calculate depth in a single sample stereo video file desk_1280x720.yuv in YUV422 format as input and single frame Disparity_640x720.yuv in YUV422 format as output, indicating the depth of objects.

Key Concepts:

• Video processing from file to file
• Bottom Up methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.

Select the "File IO Stereo Block Matching" template an compile for Linux target as project te24. Copy result to root of SD card. Copy also the input file desk_1280x720.yuv (1 843 200 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te24.elf

The Disparity_640x720.yuv file is generated and stored on the SD card. It contains one 640x720 frame in YUV422 format indicating the depth of objects. Copy Disparity_640x720.yuv file to PC and visualise it in yuvplayer (size 640x720 colour YUV422) The input file desk_1280x720.yuv can be visualised by yuvplayer (size 1280x720 colour YUV422). It contains side by side two colour frames from a stereo camera.

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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