Page History

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• Xilinx Kintex-7 XC7K160T, XC7K325T or XC7K410T FPGA SoC
• Large number of configurable I/Os are provided via HPC FMC connector
  • 4 GTX high-performance transceiver
  • 2x MGT transceiver clock inputs
  • 160 FPGA I/O's (80 LVDS pairs)
• Si5338A programmable quad PLL clock generator for GTX transceiver clocks
• On-board high-efficiency switch-mode DC-DC converters
• Lattice MachXO2 LCMXO2-1200HC System Controller CPLD
• 10x User LEDs
• PCI Express x8 connector with 4 lane PCIe Gen 2 interface
• ANSI Vita 57.1 FMC High Pin Count (HPC) connector
• DDR3 SODIMM SDRAM socket with 64bit databus width
• 256Mbit (32MByte) Quad SPI Flash memory (for configuration and operation) accessible through:
  • FPGA
  • JTAG port (SPI indirect, bus width x4)
• FPGA configuration through:
  • JTAG connector
  • Quad SPI Flash memory

• Clocking

  • Si5338 Si5338 programmable quad PLL clock generator - 4 output PLLs, GT outputs for MGT and PL clocks

  • 200MHz oscillator for DDR3 bank

• System management and power sequencingAES bit-stream encryption
  eFUSE bit-stream encryption
  
  

Additional assembly options are available for cost or performance optimization upon request.

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Table 7: Quad SPI interface signals and connections

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