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The TEF1001 FPGA board is a PCI Express card designed to fit into systems with PCI Express x8 slots and has a data transmission capability which meets PCIe Gen. 2 with 4 GTX lanes connected to the PCIe interface.
See next section for the overview of FPGA MGT lanes routed to the PCIe interface.

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Table below describes the functionalities of the switches of DIP-switches S3 and S4 at their each positions:

DIP-switch S3Signal Schematic NameConnected toFunctionalityNotes
S1-1JTAG_ENSC CPLD U5, bank 1, pin 82enables JTAG interface of SC CPLD U5SC CPLD programmable through JTAG connector, J8
S1-2VID0_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 71set 3-bit code to set FMC_VADJ voltage

The FMC_VADJ voltage is provided by DCDC U7 EN5365QI,

the voltage can be set from 0.8V to 3.3V in 7 steps, see
EN5365QI datasheet

S1-3VID1_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 63
S1-4VID2_FMC_VADJ_CTRLSC CPLD U5, bank 1, pin 62

Table 13: DIP-switch S1 functionality description

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Scroll Title
anchorFigure_4
titleFigure 4: TEF1001-02 Power-On Sequence Diagram
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Bank Voltages

BankSchematic NameVoltageRangeNotes
01V81.8V
HP: 1.2V to 1.8V
-Config bank
(
0 fixed to 1.8V
) / JTAG interface.
14
12
1V81.8V
FMC_VADJuserHR
HP
: 1.2V to
1
3.
8VQSPI flash memory interface.151V81.8V
3VFMC_VADJ voltage ajustable by DIP switch S1
13FMC_VADJuserHR
HP
: 1.2V
to 1
to 3.
8VReference clock input.
3VFMC_VADJ voltage ajustable by DIP switch S1
14
16
1V81.8V
HP
HR: 1.2V to 3.3VPL bank 14 fixed to 1.8V
I2C interface of FPGA.
15FMC_VADJuserHR
171V81.8VHP
: 1.2V
to 1
to 3.
8VReference clock input.181V81.8V
3VFMC_VADJ voltage ajustable by DIP switch S1
16VIO_B_FMCuserHR
HP
: 1.2V to 3.3VPL bank 16 fixed to 1.8V
Reference clock input / I/O's to CPLD.34VCC1V5
321V51.5VHP: 1.2V to 1.8VDDR3 memory interface
.
35
33
VCC1V5
1V51.5VHP: 1.2V to 1.8VDDR3 memory interface
.
36
34
VCC1V5
1V51.5VHP: 1.2V to 1.8VDDR3 memory interface
.114

115

116

117

118

MGTAVCC_FPGA

MGTVCCAUX

_FPGA

MGTAVTT_FPGA

1.0V

1.8V

1.2V

MGT bank supply voltage

MGT bank auxiliary supply voltage

MGT bank termination circuits voltage

MGT banks with Xilinx GTH transceiver units.191V81.8VHP: 1.2V to 1.8VI/Os routed to FMC, usable as LVDS pairs. 371V81.8VHP: 1.2V to 1.8VI/Os routed to FMC, usable as LVDS pairs. 381V81.8VHP: 1.2V to 1.8VI/Os routed to FMC, usable as LVDS pairs. 39VIO_B_FMCuserHP: 1.2V to 1.8VI/Os routed to FMC, usable as LVDS pairs.

Table 15: Module power rails

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_FPGA

MGTAVTT_FPGA

1.0V

1.8V

1.2V

MGT bank supply voltage

MGT bank auxiliary supply voltage

MGT bank termination circuits voltage

MGT banks with Xilinx GTX transceiver units

Table 15: Board I/O bank voltages

Power Rails

Connector / PinVoltageDirectionNotes
J4, pin 212V
(filtered)
Output4-wire PWM fan connector supply voltage
J6, pin 25V
(filtered)
OutputCooling fan M1 supply voltage
J8, pin 6
3V3PCI
3V3OutputVCCIO CPLD JTAG
J9, pin 21V8OutputVCCIO FPGA JTAG
J2, pin C35 / C3712VOutput
VCCIO
FMC supply voltage
J2, pin D32
3V3PCI
3V3OutputVCCIO FMC
J2, pin D36 / D38 / D39 / D403V3FMCOutputVCCIO FMC
J2, pin H1VREF_A_M2CInputVREF voltage for bank
37
13 /
38
15
J2, pin K1VREF_B_M2CInputVREF voltage for bank
39
16
J2, pin J39 / J40VIO_B_FMCInputPL I/O voltage bank
39
16 (VCCO)
J2, pin H40 / G39 / F40 / E39FMC_VADJ
OutputVCCIO FMC (fixed to 1.8V
OutputPL I/O voltage bank 12 / 13 / 15 (VCCO)
J1, pin
A10 / A11 / B8
B1 / B2 / B3 / A2 / A312V_input_B
3V3PCI
Input
PCIe interface supply voltage
12V main power supply from PCIe connector
J5, pin 1 / 2 / 312V_input_AInputMain power supply connector

Table 16: Module PL I/O bank voltages Board power rails

Variants Currently In Production

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85
ParameterMinMaxUnitsReference Document
VIN supply voltage11.412.6V12V nominal, ANSI/VITA 57.1 power specification for FMC connector
Supply voltage for HR I/O banks (VCCO)1.140

3.465

VXilinx datasheet DS182

Supply voltage for HP I/O banks (VCCO)

1.140

1.890

VXilinx datasheet DS182

I/O input voltage for HR I/O banks

–0-0.500

VCCO + 0.20VXilinx datasheet DS182
I/O input voltage for HP I/O banks–0-0.500VCCO + 0.20VXilinx datasheet DS182
Differential input voltage-0.22.625VXilinx datasheet DS182
I/O input voltage for SC CPLD U5-0.33.6VLattice MachXO2 Family datasheet
Voltages on LTM4676 I²C pins (LTM_SCL, LTM_SDA), header J1003.3VVLTM4676A datasheet

Industrial Module Board Operating Temperature Range

-4085°CXilinx datasheet DS182Commercial Module Operating Temperature Range0°CXilinx DS182, Silicon Labs Si5338 datasheets

Table 18: Module recommended operating conditions

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  • Board size: 50 mm × 40 mm. Please download the assembly diagram for exact numbers.

  • PCB thickness: ca. 1.55 mm.

  • The board meets the PCIe standard specifications for the dimensions of a PCIe cardCard Electromechanical specifications Revision 1.1

All dimensions are given in millimeters.

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