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1. Set TE0701-06 carrier board FMC_VADJ = 3.3V by switch S4:
   
   

   S4	Setup
   S4_1	ON
   S4_2	ON
   S4_3	ON
   S4_4	OFF

   
   
   

2. Set FMC_VADJ (set in step 1 to 3.3V) to drive both, the VIOTA and VIOTB by this arrangement of J16, J17 and J21.
   
   

   Jumper	Configuration
   J6	Short 1-2
   J17	no connection
   J21	Short 2-3

   
   VIOTA will provide 3.3V to PMOD J5 and FMC_VADJ will provide 3.3V to PMOD J6
   
   

3. Set switch S3  of the TE0701-06 carrier board to:
   
   

   S3	Setup
   S3_1	any
   S3_2	any
   S3_3	ON
   S3_4	OFF

   
   S3_1 and S3_2 serve as general purpose pins connected to the CPLD on the TE0701-06.
   
   

   Info
   title IMPORTANT
   Before connecting to TEC0053-04 by PMOD 12pin cables, power on the  TE0701-06 (12V) and measure presence of the 3.3V voltage on the TE0701-06 PMOD J5 pin 12 and pin 6 and on the TE0701-06 PMOD J6 pin 12 and pin 6.

4. Connect TEC0053 to two 3.3V PMOD connectors on TE0701 carrier with two 
   Pmod 12-pin cables as shown in following image.
   
   
   
   
   

5. Connect of motor rotation encoder as shown in following figure
   
   
   

   Motor rotation encoder is connected to the TEC0053-04 - EDPS Power Stage Pmod 6 pin cable connector kit. See the orientation and position of the 5 wire connection. There are 6 pins on the TEC0053-04 board. There are only 5 pins on the motor encoder. Pin 1 connects to pin 1. 6-th wire is unconnected on the motor encoder side.   

   3-phase of the motor phases are connected to the TEC0053-04 - EDPS Power Stage points A, B and C:
   A: green wire; B: red wire; C: black wire.

   All other motor wires are unused.
   The  TEC0053-04 - EDPS Power Stage can be powered by 12 V  from the power supply by separate wire connecting of the point labled “PWR” (see above) with the fused point labled “+DC” (see the first picture).
   
   

   Description of connections of TE0701 with TEC0053-04
   
   

   Code Block
   language perl
   # First PMOD cable 12-pin: # Connections of # TE0701-06 J5 with TEC0053 J9 set_property PACKAGE_PIN W18 [get_ports {SDV}]; #TE0701-06 J5:7 with TEC0053 J9:7 set_property PACKAGE_PIN W17 [get_ports {ENC_A}]; #TE0701-06 J5:8 with TEC0053 J9:8 set_property PACKAGE_PIN Y19 [get_ports {ENC_B}]; #TE0701-06 J5:9 with TEC0053 J9:9 set_property PACKAGE_PIN AA19 [get_ports {ENC_I}]; #TE0701-06 J5:10 with TEC0053 J9:10 # GND #TE0701-06 J5:11 with TEC0053 J9:11 # 3,3V #TE0701-06 J5:12 with TEC0053 J9:12 set_property PACKAGE_PIN Y16 [get_ports {SCLK}]; #TE0701-06 J5:1 with TEC0053 J9:1 set_property PACKAGE_PIN W16 [get_ports {SDI1}]; #TE0701-06 J5:2 with TEC0053 J9:2 set_property PACKAGE_PIN Y18 [get_ports {SDI2}]; #TE0701-06 J5:3 with TEC0053 J9:3 set_property PACKAGE_PIN AA18 [get_ports {SDI3}]; #TE0701-06 J5:4 with TEC0053 J9:4 #GND #TE0701-06 J5:5 with TEC0053 J9:5 #3,3V #TE0701-06 J5:6 with TEC0053 J9:6 #All signals connected by the first PMOD cable cable belong to TE0720 Zynq Bank 33. # Second PMOD cable 12-pin: # Connections of #TE0701-06 J6 with TEC0053 J8 set_property PACKAGE_PIN Y8 [get_ports {GL[0]}]; #TE0701-06 J6:7 with TEC0053 J8:7 set_property PACKAGE_PIN Y9 [get_ports {GL[1]}]; #TE0701-06 J6:8 with TEC0053 J8:8 set_property PACKAGE_PIN V9 [get_ports {GL[2]}]; #TE0701-06 J6:9 with TEC0053 J8:9 #GND #TE0701-06 J6:11 with TEC0053 J8:11 #3,3V #TE0701-06 J6:12 with TEC0053 J8:12 set_property PACKAGE_PIN AA7 [get_ports {GH[0]}]; #TE0701-06 J6:1 with TEC0053 J8:1 set_property PACKAGE_PIN AA6 [get_ports {GH[1]}]; #TE0701-06 J6:2 with TEC0053 J8:2 set_property PACKAGE_PIN U11 [get_ports {GH[2]}]; #TE0701-06 J6:3 with TEC0053 J8:3 #GND #TE0701-06 J6:5 with TEC0053 J8:5 #3,3V #TE0701-06 J6:6 with TEC0053 J8:6 # Second PMOD Cable 12-pin contains these two wires unconnected to the SDSoC design: #set_property PACKAGE_PIN V10 [get_ports {gpio_0_tri_io[0]}]; #TE0701-06 J6:10 - TEC0053 J8:10 #set_property PACKAGE_PIN U12 [get_ports {gpio_0_tri_io[1]}]; #TE0701-06 J6:4 - TEC0053 J8:4 #All signals connected by the second Pmod cable belong to TE0720 Zynq Bank 13.

   Info
   title NOTEOlder Carrier Board Revisions
   The older TE0701-04 or TE0701-05 carrier boards can be used with the identical platform, but  the setup for generation of 3.3V on the PMOD J5 and PMOD J6 is different. There is no S4 switch and the FMC_VADJ = 3.3 V needs to be set by switch S3. Set switch S3 of the TE0701-04 or TE0701-05 carrier board to: S3_1 OFF; S3_2 ON; S3_3 ON; S3_4 OFF   Arrange jumpers J17 and J21: J17: [1,2,3] connect 1-2 J21: [1,2,3] connect 2-3 Fixed 3.3V will go to PMOD J5. FMC_VADJ will provide 3.3V to PMOD J6Before connecting to TEC0053-04 by PMOD 12pin cables, power on (12V) the  TE0701-04 or the TE0701-05 carrier board and measure presence of the 3.3V voltage on the TE0701-06 PMOD J5 pin 12 on pin 6 and presence of the 3.3V voltage coming from the adjustable FMC_VADJ on the TE0701-04 or TE0701-05 PMOD J6 pin 12 and pin 6.

   
   
   

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1. Unzip Reference Design
   
   IMPORTANT: Do not change base folder name after extraction!
                         <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\zsys\
   
   
2. CD to the directory and run from win terminal:
   _create_win_setup.cmd
   
   run from win terminal:
   _use_virtual_drive.cmd
   reply to select an virtual drive name (example X): X
   reply: 0
   
   cd X:\zsys
   
   This is shortest possible path and directory name for building of the platform
   in windows (to respect the 260 character limitations.)
   
   NOTE: Do not change the name of the directory /zsys
   It has to be identical to the shortest possible platform name “zsys”
   for the Zynq 7000 targets.
   
   

3. Enable SDSOC, set install path of Xilinx tools, set your hardware assembly option in: "design_basic_settings.cmd" Select one of these supported modules (1,4,5,6,7):

   
   1           

   
   
   

   ID	TE Module
   1	te0720-03-

   2if  

   2if

   4

   4           

   te0720-03-l1if

   5           

   5	te0720-03-1cf
   6

   6           

   te0720-03-2ef

   7

   7           

   te0720-03-07s

            
   NOTE:  Selection 7 supports the TE0720-03-14S-1C module (xc7z014sclg484-1c device).
   
   

4.  Create Reference Design: run "vivado_create_project_guimode.cmd"
   
   
5. VIVADO:

1. TCL-Console type: TE::hw_build_design -export_prebuilt

2. Find hardware handoff file .hdf under prebuilt folder abd copy it to Ubuntu 16.04, with Petalinux 2017.1.

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1. Info
   title IMPORTANT
   Before petalinux project can be built, the executable rights must be set for these files: ./init_config.sh ./project-spec/meta-user/recipes-apps/libuv/files/checksparse.sh ./project-spec/meta-user/recipes-apps/libuv/files/gyp_uv.py ./project-spec/meta-user/recipes-apps/libuv/files/autogen.sh ./project-spec/meta-user/recipes-apps/libuv/files/android-configure ./project-spec/meta-user/recipes-apps/libuv/update-src.sh

   In Ubuntu 16.04, build Petalinux image image.ub and uboot u-boot.elf using Petalinux BSP provided under os folder and place new images to correct subfolder in prebuilt/os

2. TCL-Console type: TE::sw_run_hsi
3. TCL-Console type:TE::ADV::beta_util_sdsoc_project

1. Vivado project will be modified by copying constrain files locally to project.
   
   NOTE: If needed, recreate project with batch file to restore original Vivado project with externally linked constrains.
1. Wait for project creation:
2. SDSoC Platform is created
in 
3. in  

1. 1. X:\zsys\SDSoC_PFM\<TE::SHORTDIR>\zsys
   2. Copy
      X:\zsys\_use_virtual_drive.cmd
      to
      X: \SDSoC_PFM\<TE::SHORTDIR>\zsys
   3. Copy these two files from:
      X:\zsys\init.sh
      X:\zsys\focserver.conf
      to
      X:\SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\linux\image\init.sh
      X:\SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\linux\image\focserver.conf
   4. Copy directory with all files from:
      X:\zsys\misc\src\
      to
      X: \SDSoC_PFM\<TE::SHORTDIR>\zsys\src\
   5. Copy directory with all files from:
      X:\zsys\misc\sw\aarch32-linux\
      X:\zsys\misc\sw\aarch32-none\
      to
      X: \SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\aarch32-linux\
      X: \SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\ aarch32-none\
   1. Close current Vivado project
   2. Clear working project files by script
      X:\zsys\design_clear_design_folders.cmd
   3. From win terminal, execute:
      _use_virtual_drive.cmd
      reply to select an virtual drive name (example X): X
      reply: 1
      This will disconnect the virtual X: drive
   4. Compile support libraries serving for connection to 64bit AXI I/O.
      Open the SDx Terminal 2017.1
      CD to: <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\
      In the SDx Terminal 2017.1, run batch file:
      build_linux.bat
      Library for the SDSoC Linux target is created:
      <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\libte0720_foc.a
      Move the created library libte0720_foc.a to
      <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\aarch32-linux\lib\libte0720_foc.a
      Delete the created _sds directory
      <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\_sds
      
      In the SDx Terminal 2017.1, run batch file:
      build_standalone.bat
      Library for the SDSoC standalone target is created:
      <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\libte0720_foc.a
      Move the created library libte0720_foc.a to
      <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\sw\aarch32-none\lib\ libte0720_foc.a
      Delete the created _sds directory
      <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>\zsys\src\_sds
      The SDSoC platform for the target \<TE::SHORTDIR> is in
      <install_path>\TE0701_zsys_SDSoC_EDDP_FOC\SDSoC_PFM\<TE::SHORTDIR>
      
      Close the SDx Terminal 2017.1 

Set TE SDSoC Platform as local SDSoC Platform

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