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DateVivadoProject BuiltAuthorsDescription
2018-09-042018.2TE0807-test_board_noprebuilt-vivado_2018.2-build_03_20180904121458.zip
TE0807-test_board-vivado_2018.2-build_03_20180904121522.zip
John Hartfiel
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-01-182017.4TE0807-test_board_noprebuilt-vivado_2017.4-build_05_20180118152119.zip
TE0807-test_board-vivado_2017.4-build_05_20180118152104.zip
John Hartfiel
  • rework Board Part Files

2017-11-14

2017.2TE0807-test_board_noprebuilt-vivado_2017.2-build_05_20171114115524.zip
TE0807-test_board-vivado_2017.2-build_05_20171114115511.zip
John Hartfiel
  • initial release

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SoftwareVersionNote
Vivado2017.48needed
SDK2017.48needed

Hardware

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0807-01-ES2 es2REV012GB64MB

Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.

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Reference Design is available on:

Design Flow

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Basic Design Steps
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TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality 


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which did not ends with *_tebf0808
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

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For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

Xilinx default FSBL

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  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation

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hello_te0807

Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.

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DateDocument RevisionAuthorsDescription

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  • Release 2018.2

v.5John Hartfiel
  • Release 2017.4
2017-11-14v.3John Hartfiel
  • Release 2017.2

All

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Legal Notices

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