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titleTable 1: Design Revision History

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DateVivadoProject BuiltAuthorsDescription
2018-09-132018.2TEC0850-test_board-vivado_2018.2-build_03_20180913143619.zip
TEC0850-test_board_noprebuilt-vivado_2018.2-build_03_20180913143635.zip
Oleksandr Kiyenko, John Hartfielinitial release

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For general structure and of the reference design, see Project Delivery - AMD devices

Design Sources

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titleTable 7: Design sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration
SDSoC<design name>/../SDSoC_PFMSDSoC Platform will be generated by TE Scripts or as separate download

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Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality


  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

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Note:

  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz
    • only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

GTH Transceiver with Aurora IP:

  • MGT Control: looback, PMA Init, Power Down, Reset... see: ug576-ultrascale-gth-transceivers
    • Loopback 2 is Near-end PMA Loopback, if no lane is connected, 0 for normal operation
    • Set PMA Init one time after changing
  • Channel up is link status for the lanes
  • PLL GTP lock status of GTH PLLs,

LED

  • Control of front panel user LEDs

FMeter

  • Measurement of different CLKs
  • Note: USB CLK is only available if USB 3 is connected.


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titleFigure 1: Vivado Hardware Manager
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System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

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Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

/* ETH PHY */

&gem0 {
    phy-handle = <&phy0>;
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};



/* USB 2.0 */
 
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
};
 
&dwc3_1 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
};
 


/* SD*/

&sdhci1 {
    disable-wp;
    no-1-8-v;
};

/* SPI */
// &spi0 {
//     num-cs = <1>;
//     ext_command:spidev@0{
//         compatible="spidev";
//         reg = <0>; //chipselect 0
//         spi-max-frequency= <100000>;
//         spidev-name = "EXT";
//     };
// };
// 

/* I2C */
// &i2c0 {
//     #address-cells = <1>;
//     #size-cells = <0>;
// };

&i2c1{  // TEC0850
    #address-cells = <1>;
    #size-cells = <0>;
    // Instantiate EEPROM driver
    eeprom153: eeprom@53 {
        compatible = "atmel,24c02";
        reg = <0x53>;
    };
    // Instantiate EEPROM driver
    eeprom150: eeprom@50 {
        compatible = "atmel,24c128";
        reg = <0x50>;
    };
    // There is also Clock generator chip
    // Si5345 at address 0x69, but there is
    // no standard driver in Linux kernel yet
};


Kernel

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Deactivate:

  • CONFIG_CPU_IDLE      (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ    (only needed to fix JTAG Debug issue)

Rootfs

Activate:

  • i2c-tools

Applications

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