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DDR3 SDRAM
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ECC SO-DIMM Socket
The TEF1001 board supports additional DDR3 SODIMM ECC SO-DIMM via 204-pin socket U2. The DDR3 memory interface has a 64bit wide databus and is routed to the FPGA banks 32, 33 and 34.
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There is also a I2C interface between the System Controller CPLD U5 and the DDR3 SODIMM ECC SO-DIMM memory socket U2.
| I²C Interface | Schematic net names | Connected to | I²C Address | Notes |
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| DDR3 SODIMM, U2 | 'DDR3_SDA', pin 200 | SC CPLD U5, pin 42 | module dependent | - |
Table 12: DDR3 SODIMM socket I²C interface
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It is important to use SO-DIMMs which also provide ECC functionality. Otherwise the SO-DIMM is not compatible with this board. |
Quad SPI Flash Memory
A 256 Mbit (32 MByte) Quad SPI Flash Memory (Micron N25Q256A, U12) is provided for FPGA configuration file storage. After configuration process completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency. The memory can be accessed indirectly by the FPGA JTAG port (J9) by implementing the functional logic for this purpose inside the FPGA.
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