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Scroll Title
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titleFigure 1: TEF1001-02 block diagram
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titleFigure 2: TEF1001-02 main components
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  1. Xilinx Kintex XC7K-2FBG676I FPGA SoC, U6
  2. ANSI/VITA 57.1 compliant FMC HPC connector, J2
  3. Cooling fan 5VDC M1 (45X5MM, 0.7W, 1.06CFM), M1
  4. PCIe x8 connector, J1
  5. DDR3 SODIMM 204-pin socket, U2
  6. 6-pin 12V power connector, J5
  7. Step-down DC-DC converter @1.5V and @4V (LT LTM4676A), U3
  8. Step-down DC-DC converter @1.0V (LT LTM4676A), U4
  9. 256 Mbit Quad SPI Flash Memory (Micron N25Q256A), U12
  10. 10x Green user LEDs connected to FPGA, D1 ... D10
  11. 4-wire PWM fan connector, J4
  12. User button, S2
  13. FPGA JTAG connector, J9
  14. 4bit DIP switch, S1
  15. I²C header for LTM4676A DC-DC converter, J10
  16. System Controller CPLD JTAG header, J8
  17. 1x Green LED connected to SC CPLD, D11
  18. 2-pin 5V FAN header, J6
  19. System Controller CPLD (Lattice Semiconductor LCMXO2-1200HC), U5
  20. 6A PowerSoC DC-DC converter @FMC_VADJ (Altera EN5365QI), U7
  21. 4A PowerSoC DC-DC converter @3.3V (3V3FMC) (Altera EN6347QI), U15
  22. LDO converter @1.2V (MGTAVTT_FPGA) (TI TPS74401RGW), U17
  23. LDO converter @1.0V (MGTAVCC_FPGA) (TI TPS74401RGW), U18
  24. 4A PowerSoC DC-DC converter @1.8V (Altera EN6347QI), U7

Initial Delivery State

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titleInitial delivery state of programmable devices on the module

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Storage device nameContentNotes
Si5338A OTP Areanot programmed-

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

demo design

-
HyperFlash Memorynot programmed-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-

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Table 1: Initial delivery state of programmable devices on the module

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Control Signals

To get started with TEF1001 board, some basic control signals are essential and are described in the following table:

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titleTE0701 Control Signals

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Control signal

Switch / Button / LED / PinSignal Schematic Names

Connected to

Functionality

Notes
SC CPLD JTAG EnableDIP switch S3-3JTAGENSC CPLD U14, pin 82

ON: SC CPLD JTAG enabled,
OFF: FPGA JTAG enabled

-
BOOT MODESC CPLD U14, pin 27MODEB2B JB1, pin 31Boot Mode for attached module (Flash or SD)-
Module ResetSC CPLD U14, pin 13RESINB2B JB2, pin 17Module Reset-
Global Reset inputPush Button S2S2SC CPLD U14, pin 2Manual reset from user-
SD Card detectionSD Slot J8, pin 10SD_DETECTSC CPLD U14, pin 40Detection Signal for inserted SD CardBoot mode is set to SD Boot,
when SD Card is detected.
Board status indicatorsRed LEDs D1 ... D8ULED1 ... ULED8SC CPLD U14, pins
78, 77, 76, 16, 69, 68, 65, 64		indicating various board and
module status / configuration		Refer to the firmware documentation of the SC CPLD
U14 and to the subsection 'LEDs' in section 'On-board Peripherals'
for more details and current functionality.
Board 3.3V power indicatorGreen LED D223V3INB2B JB1, pin 14, 16

ON: 3.3V on-board voltage available

-
FMC_VADJ voltage selectionDIP switches S4-1, S4-2, S4-3VID0 ... VID2SC CPLD U14, pins 34, 35, 38sets adjustable voltage for FMC connector-
I²C control / FMC_VADJ voltage selectionDIP switches S3-2, S3-1CM0, CM1SC CPLD U14, pins 99, 1enabling / disabling I²C control of board functionalities,
sets FMC_VADJ voltage (only 3 steps),
available to user if FMC_VADJ set by DIP-switch S4		Refer to the firmware documentation of the SC CPLD
U14 and and to the subsection 'DIP switches' in section 'On-board
Peripherals' for current functionality and more details.


By default the configuration mode pins M[2:0] of the FPGA are set to QSPI mode (Master SPI), hence the FPGA is configured from QSPI Flash memory at system start-up. The JTAG interface of the module is provided for storing the initial FPGA configuration data to the QSPI Flash memory.

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I/O signals and interfaces connected to the FPGA SoCs I/O bank and FMC connector J2:

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J2
InterfacesI/O Signal CountLVDS-pairs countConnected toVCCO bank VoltageNotes
I/O4824FPGA Bank 12 HRFMC_VADJBank voltage FMC_VADJ is supplied by DC-DC converter U7
3417FPGA Bank 13 HRFMC_VADJ
3417FPGA Bank 15 HRFMC_VADJ
4444FPGA Bank 16 HRVIO_B_FMCBank voltage VIO_B_FMC is supplied by FMC connector J2
I²C2-SC CPLD U5, Bank 2, pin 48, 49-FMC connector J2 is hardware programmed to I²C address 0x50
JTAG5-SC CPLD U5, Bank 2, pin 27, 28, 331, 32 ,363.3V-4 JTAG pins with additional signal 'TRST'
MGT-8 (4 x RX/TX)Bank 116 GTX-4x MGT lanes
Clock Input-2Bank 116 GTX-2x Reference clock input to MGT bank
Control Signals3-SC CPLD U5, Bank 1, pin 68, 69 ,703.3V

'FMC_PG_C2M', 'FMC_PG_M2C', 'FMC_PRSNT_M2C_L'

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FMC connector J2 MGT Lanes:

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J2
MGT LaneBankTypeSignal Schematic NameFMC Connector PinFPGA Pin
0116GTX
  • DP3_M2C_P
  • DP3_M2C_N
  • DP3_C2M_P
  • DP3_C2M_N
  • J2-A10
  • J2-A11
  • J2-A30
  • J2-A31
  • MGTXRXP0_116, G4
  • MGTXRXN0_116, G3
  • MGTXTXP0_116, F2
  • MGTXTXN0_116, F1
1116GTX
  • DP2_M2C_P
  • DP2_M2C_N
  • DP2_C2M_P
  • DP2_C2M_N
  • J2-A6
  • J2-A7
  • J2-A26
  • J2-A27
  • MGTXRXP1_116, E4
  • MGTXRXN1_116, E3
  • MGTXTXP1_116, D2
  • MGTXTXN1_116, D1
2116GTX
  • DP1_M2C_P
  • DP1_M2C_N
  • DP1_C2M_P
  • DP1_C2M_N
  • J2-A2
  • J2-A3
  • J2-A22
  • J2-A23
  • MGTXRXP2_116, C4
  • MGTXRXN2_116, C3
  • MGTXTXP2_116, B2
  • MGTXTXN2_116, B1
3116GTX
  • DP0_M2C_P
  • DP0_M2C_N
  • DP0_C2M_P
  • DP0_C2M_N
  • J2-C6
  • J2-C7
  • J2-C2
  • J2-C3
  • MGTXRXP3_116, B6
  • MGTXRXN3_116, B5
  • MGTXTXP3_116, A4
  • MGTXTXN3_116, A3

...

FMC connector J2 reference clock sources:

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J2
Signal Schematic NameConnected toFMC Connector PinFPGA PinNotes
  • GBTCLK0_M2C_P
  • GBTCLK0_M2C_N
MGT bank 116

J2-D4
J2-D5

MGTREFCLK0P_116, D6
MGTREFCLK0N_116, D5

Supplied by attached FMC module
  • GBTCLK1_M2C_P
  • GBTCLK1_M2C_N
MGT bank 116J2-B20
J2-B21		MGTREFCLK1P_116, F6
MGTREFCLK1N_116, F5		Supplied by attached FMC module

...

FMC connector J2 VCC/VCCIO:

...

J2
Available VCC/VCCIOFMC Connector PinSourceNotes
3V3FMC

J2-D36
J2-D38
J2-D40
J2-C39

DCDC U15,
max. current: 4A

Enable by SC CPLD U5, bank 1, pin 60
Signal: 'EN_3V3FMC'

3V3

J2-D32

LDO U9,

max. current: 0.5A		not dedicated for FMC connector
12V

J2-C35
J2-C37

external source through
ATX main power connector

-
FMC_VADJ

J2-H40
J2-G39
J2-F40
J2-E39

DCDC U7,
max. current: 6A

Enable by SC CPLD U5, bank 1, pin 51
Signal: 'EN_FMC_VADJ'

set voltage FMC_VADJ by DIP switch S1

...

FMC connector J2 Cooling Fan:

...

J2
Fan DesignatorEnable SignalNotes
M1

Enable by SC CPLD U5, bank 0, pin 78
Signal: 'FAN_FMC_EN'

-

...


Following table lists lane number, MGT bank number, transceiver type, signal schematic name, connector and FPGA pins connection:

...

LaneBankTypeSignal NamePCIe Connector PinFPGA Pin
J10115GTX
  • PER3_P
  • PER3_N
  • PET3_P
  • PET3_N
  • J1-A29
  • J1-A30
  • J1-B27
  • J1-B28
  • MGTXTXP0_115, P2
  • MGTXTXN0_115, P1
  • MGTXRXP0_115, R4
  • MGTXRXN0_115, R3
1115GTX
  • PER2_P
  • PER2_N
  • PET2_P
  • PET2_N
  • J1-A25
  • J1-A26
  • J1-B23
  • J1-B24
  • MGTXTXP1_115, M2
  • MGTXTXN1_115, M1
  • MGTXRXP1_115, N4
  • MGTXRXN1_115, N3
2115GTX
  • PER1_P
  • PER1_N
  • PET1_P
  • PET1_N
  • J1-A21
  • J1-A22
  • J1-B19
  • J1-B20
  • MGTXTXP2_115, K2
  • MGTXTXN2_115, K1
  • MGTXRXP2_115, L4
  • MGTXRXN2_115, L3
3115GTX
  • PER0_P
  • PER0_N
  • PET0_P
  • PET0_N
  • J1-A16
  • J1-A17
  • J1-B14
  • J1-B15
  • MGTXTXP3_115, H2
  • MGTXTXN3_115, H1
  • MGTXRXP3_115, J4
  • MGTXRXN3_115, J3

...

FAN Connectors

The TEF1001 board offers two one FAN connectors connector for cooling the FPGA device and on one built-in FAN for the FMC modules.

ConnectorSignal Schematic net namesNamesConnected toNotes
4-Wire PWM FAN
connector J4,
12V power supply

'F1SENSE', pin J4-3
'F1PWM', pin J4-4

SC CPLD U5, pin 99
SC CPLD U5, pin 98

FPGA cooling FAN can be controlled via
I²C interface from FPGA,
see current SC CPLD firmware
2-pin FAN connector J6,
5V power supply
with TPS2051 Load Switch U25

'FAN_FMC_EN',

(Load Switch U25, pin 4)

SC CPLD U5, pin 78

FMC cooling FAN

...

Pin NameSC CPLD DirectionFunctionDefault Configuration
200MHZCLK_ENoutcontrol lineenables 200.0000MHz oscillator U1
BUTTONinuserReset Button
CPLD_TDOoutCPLD JTAG interface



-
CPLD_TDIin
CPLD_TCKin
CPLD_TMSin
JTAG_ENin
DDR3_SCLin / outI²C bus of DDR3 SODIMM socket

I²C connected to FPGA
DDR3_SDAin / out
PLL_SCLin / outI²C bus of SI5338 quad clock PLLI²C connected to FPGA
PLL_SDAin / out
PCIE_RSTBinPCIe reset inputsee refer to current SC CPLD firmware
FEX_DIR / FEX0 ... FEX11in / outuser GPIOsee refer to current SC CPLD firmware
F1PWMoutFPGA FAN controlsee refer to current SC CPLD firmware
F1SENSEin
FAN_FMC_ENoutFMC FAN enable
FMC_PG_C2MoutFMC signals and pinssee refer to current SC CPLD firmware
FMC_PG_M2Cin
FMC_PRSNT_M2C_Lin
FMC_SCLin / outFMC I²CI²C connected to FPGA
FMC_SDAin / out
FMC_TCK
FMC JTAGsee refer to current SC CPLD firmware
FMC_TDI
FMC_TDO
FMC_TMS
FMC_TRST
DONEinFPGA configuration signalPL configuration completed
PROGRAM_BoutPL configuration reset signal
LED1outLED status signalsee refer to current SC CPLD firmware
FPGA_IIC_OEinSC CPLD works as I²C switch
with the FPGA as I²C-Master
and on-board peripherals as
I²C-slaves		I²C output enable, connected to PL bank 14 pin F25
FPGA_IIC_SCLin / outI²C clock line, connected to PL bank 14 pin G26
FPGA_IIC_SDAin / outI²C data line, connected to PL bank 14 pin G25
EN_1V8outPower controlenable signal DCDC U20 '1V8'
PG_1V8inpower good signal DCDC U20 '1V8'
EN_3V3FMCoutenable signal DCDC U15 'EN_3V3FMC'
PG_3V3inpower good signal U15 'EN_3V3FMC'
EN_FMC_VADJoutenable signal DCDC U7 'FMC_VADJ'
PG_FMC_VADJinpower good DCDC U7 'FMC_VADJ'

VID0_FMC_VADJ,
VID1_FMC_VADJ,
VID2_FMC_VADJ

outDCDC U7 power selection pin

VID0_FMC_VADJ_CTRL,
VID1_FMC_VADJ_CTRL,
VID2_FMC_VADJ_CTRL

inPower selection of FMC_VADJ, forwarded
to DCDC U7
LTM_1V5_RUNoutenable signals of DCDC U3, U4 (LTM4676)
see refer to current SC CPLD firmware
LTM_4V_RUNout
LTM_SCLin / outDCDC U3, U4 (LTM4676) I²C

I²C Address U3: 0x40

I²C Address U4: 0x4F

I²C interface of LTM4676 ICs
also accessible through header J10

LTM_SDAin / out
LTM1_ALERTinDCDC U3, U4 (LTM4676) control,
active low		see refer to current SC CPLD firmware
LTM2_ALERTin
LTM_1V_IO0in / out
LTM_1V_IO1in / out
LTM_1V5_4V_IO0in / out
LTM_1V5_4V_IO1in / out

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