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| SC CPLD U5 Pins and Interfaces | Connected to | Function | Notes |
|---|---|---|---|
| 200MHZCLK_EN | Oscillator U1, pin 1 | Oscillator U1 control line | enables 200.0000MHz oscillator U1 |
| BUTTON | Push Button S2 | user | Reset Button |
| CPLD_JTAG_TDO | header J8, pin 3 | SC CPLD JTAG interface | SC CPLD JTAG interface enabled when DIP-switch S1-1 in ON-position |
| CPLD_JTAG_TDI | header J8, pin 2 | ||
| CPLD_JTAG_TCK | header J8, pin 4 | ||
| CPLD_JTAG_TMS | header J8, pin 1 | ||
| JTAG_EN | DIP switch S1-1 | ||
| DDR3_SCL | SO-DIMM U2. pin 202 | I²C bus of DDR3 SO-DIMM socket | I²C bus connected to FPGA |
| DDR3_SDA | SO-DIMM U2. pin 200 | ||
| PLL_SCL | Si5338 U13, pin 12 | I²C bus of SI5338 quad clock PLL | I²C bus connected to FPGA |
| PLL_SDA | Si5338 U13, pin 19 | ||
| PCIE_RSTb | PCIe J1, pin A11 | PCIe reset input | refer to current SC CPLD firmware for functionality |
| FEX_DIR / FEX0 ... FEX11 | FPGA bank 14 | user GPIO | refer to current SC CPLD firmware for functionality |
| F1PWM | FAN connector J4, pin 4 | FPGA FAN control | refer to current SC CPLD firmware for functionality |
| F1SENSEin | FAN connector J4, pin 3 | ||
| FAN_FMC_ENout | Load Switch U25, pin 4 | FMC FAN enable | |
| FMC_PG_C2M | outFMC J2, pin D1 | FMC control signals and pins | refer to current SC CPLD firmware for functionality |
| FMC_PG_M2C | inFMC J2, pin F1 | ||
| FMC_PRSNT_M2C_L | inFMC J2, pin H2 | ||
| FMC_SCLin / out | FMC J2, pin C30 | FMC I²C | I²C connected to FPGA |
| FMC_SDAin / out | FMC J2, pin C31 | ||
| FMC_TCK | FMC J2, pin D29 | FMC JTAG | refer to current SC CPLD firmware for functionality |
| FMC_TDI | FMC J2, pin D30 | ||
| FMC_TDO | FMC J2, pin D31 | ||
| FMC_TMS | FMC J2, pin D33 | ||
| FMC_TRST | FMC J2, pin D34 | ||
| DONEin | FPGA bank 0, pin J7 | FPGA configuration signal | PL configuration completed |
| PROGRAM_Bout | FPGA bank 0, pin P6 | PL configuration reset signal | |
| LED1out | Green LED D11 | LED status signal | refer to current SC CPLD firmware for functionality |
| FPGA_IIC_OEin | FPGA bank 14, pin F25 | SC CPLD works as I²C switch with the FPGA as I²C-Master and on-board peripherals as I²C-Slaves | I²C output enable, connected to PL bank 14 pin F25 |
| FPGA_IIC_SCLin | / outFPGA bank 14, pin G26 | I²C clock line, connected to PL bank 14 pin G26 | |
| FPGA_IIC_SDAin | / outFPGA bank 14, pin G25 | I²C data line, connected to PL bank 14 pin G25 | |
| EN_1V8out | DC-DC U20 | Power control | enable signal DCDC U20, voltage '1V8' |
| PG_1V8 | in | power good signal DCDC U20, voltage '1V8' | |
| EN_3V3FMC | out | enable signal DCDC U15, voltage 'EN_3V3FMC' | |
| PG_3V3 | in | power good signal U15, voltage 'EN_3V3FMC' | |
| EN_FMC_VADJ | out | enable signal DCDC U7, voltage 'FMC_VADJ' | |
| PG_FMC_VADJ | in | power good DCDC U7, voltage 'FMC_VADJ' | |
VID0_FMC_VADJ, | out | DCDC U7 power selection pin | |
VID0_FMC_VADJ_CTRL, | in | Power selection of FMC_VADJ, forwarded to DCDC U7 | |
| LTM_1V5_RUN | out | enable signals of DCDC U3, U4 (LTM4676) refer to current SC CPLD firmware for functionality | |
| LTM_4V_RUN | out | ||
| LTM_SCL | in / out | DCDC U3, U4 (LTM4676) I²C | I²C Address U3: 0x40 I²C Address U4: 0x4F I²C interface of LTM4676 ICs |
| LTM_SDA | in / out | ||
| LTM1_ALERT | in | DCDC U3, U4 (LTM4676) control, active low | refer to current SC CPLD firmware for functionality |
| LTM2_ALERT | in | ||
| LTM_1V_IO0 | in / out | ||
| LTM_1V_IO1 | in / out | ||
| LTM_1V5_4V_IO0 | in / out | ||
| LTM_1V5_4V_IO1 | in / out |
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