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Basic Notes
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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation

Overview

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General Design description
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Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.

Key Features

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Revision History

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Release Notes and Know Issues

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Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

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Overview

Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.
Refer to http://trenz.org/te0745-info for the current online version of this manual and other available documentation.

Key Features

Revision History

Release Notes and Know Issues

Requirements

Software

Hardware

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

Design supports following carriers:

Additional HW Requirements:

Content

For general structure and of the reference design, see Project Delivery

Design Sources

Additional Sources

Prebuilt

Additional Sources

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Prebuilt

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<table width="100%">
<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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Description

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Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0745 "test Board Reference Design

Design Flow

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TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality 

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   
2. Press 0 and enter for minimum setup
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project
   
   1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
5. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (uboot.elf and image.ub) with exported HDF
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinuxNote: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
   
   1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
8. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Not used on this Example.

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Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

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2. Type on Vivado TCL Console:

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1. TE::pr_program_flash_

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1. binfile -swapp

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1. u-boot

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SD

1. 
   Note:

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1. To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
            optional "TE::pr_program_flash_binfile -swapp hello_te0745" possible

1. Copy image.ub and Bootinit.bin on SD-Cardsh (optional on /misc/sd) on SD-Card
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
2. Insert SD-Card

SD

1. Copy image.ub,Boot.bin and init.sh (optional on /misc/sd) on SD-Card.
   .
   • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
   • Set Boot Mode to SD-Boot.
     • Depends on Carrier, see carrier TRM.
   • Insert SD-Card in SD-Slot.

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1. Open Serial Console (e.g. putty)
   
   1. Speed: 115200
   2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
2. Linux Console:
   Note: Wait until Linux boot finished For Linux Login use:
   
   1. User Name: root
   2. Password: root
3. You can use Linux shell now.
   1. I2C 0 Bus type: i2cdetect -y -r 0
   2. RTC check: dmesg | grep rtc
   3. ETH0 works with udhcpc
   4. USB type  "lsusb" or connect USB2.0 device
      

Vivado HW Manager

SI5338_CLK0 Counter: 

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Note: Add picture of HW Manager add notes for the signal either groups or topics, for example: Control: add controllable IOs with short notes.. Monitoring: add short notes for signals which will be monitored only SI5338_CLK0 Counter:  Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

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Set radix from VIO signals to unsigned integer.

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Note: Frequency Counter is inaccurate and displayed unit is Hz

SI5338 CLK is configured to  125MHz by default.

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System Design - Vivado

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Block Design

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PS Interfaces

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• Monitoring:

  • SI5338_CLK0 Counter: 

    • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.
      Note: Frequency Counter is inaccurate and displayed unit is Hz, SI5338 CLK is configured to 125MHz by default.
      

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System Design - Vivado

Block Design

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PS Interfaces

Activated interfaces:

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

Design specific constrain

No additional constrains.

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

FSBL

TE modified 2018.2 FSBL

Changes:

• Si5338 Configuration see fsbl_hooks.c
• Add register_map.h, si5338.c, si5338.h

hello_te0745

Hello TE0745 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

No changes.

U-Boot

No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
};
/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    

Constrains

Basic module constrains

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]

Design specific constrain

No additional constrains.

Software Design - SDK/HSI

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optional chapter
separate sections for different apps
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For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

TE modified 2017.2 FSBL

Changes:

• Si5338 Configuration see fsbl_hooks.c
• Add register_map.h, si5338.c, si5338.h

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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optional chapter
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For PetaLinux installation and  project creation, follow instructions from:

• PetaLinux KICKstart

Config

No changes.

U-Boot

No changes.

Device Tree

/include/ "system-conf.dtsi"
/ {
};


/* ethernet */
&gem0 {
    phy-handle = <&phy0>;
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;
    status = "okay";
   phy0 flash0: phy@1flash@0 {
            compatible = "marvelljedec,88e1510spi-nor";
            device_type = "ethernet-phy"reg = <0x0>;
            reg#address-cells = <1>;
        }#size-cells = <1>;
    } ;
};


/* usbethernet */
/&gem0 {
    phy-handle = <&phy0>;
   usb_phy0: usb_phy@0 mdio {
        compatible#address-cells = "ulpi-phy"<1>;
        #phy#size-cells = <0>;
         reg = <0xe0002000 0x1000>;
phy0: phy@1 {
            view-portcompatible = <0x0170>"marvell,88e1510";
            drv-vbusdevice_type = "ethernet-phy";
    };
};

&usb0 {
        dr_modereg = "host"<1>;
    //dr_mode = "peripheral"    } ;
    usb-phy = <&usb_phy0>} ;
};

/* flashusb */
&flash0/{
    usb_phy0: usb_phy@0 {
        compatible = "micron,n25q256aulpi-phy";
    #size-cells     #phy-cells = <1><0>;
        reg = <0xe0002000 <0x0>0x1000>;
    spi-tx-bus-width    view-port = <1><0x0170>;
    spi-rx-bus-width = <4>    drv-vbus;
    spi-max-frequency = <10000000>;
};
};

/* I2C */

&i2c0usb0 {
    #address-cellsdr_mode = <1>"host";
    //dr_mode = "peripheral";
    usb-phy = <&usb_phy0>;
};


/* I2C */

&i2c0 {
    #address-cells = <1>;
    #size-cells = <0>;

    rtc0: rtc@6F {
        compatible = "isl12022";
        reg = <0x6F>;
    };


    i2cmux_SFP: i2cmux@72  {
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x72>;

        SFP@0 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        SFP@1 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
        };
        SFP@2 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        SFP@3 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        SFP@4 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        SFP@5 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        SFP@6 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        SFP@7 {
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };

};

Kernel

Activate:

• USB_ULPI_BUS
• RTC_DRV_ISL12022

Rootfs

Activate:

• i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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SI5338

Download  ClockBuilder Desktop for SI5338

1. Install and start ClockBuilder
2. Select SI5338
3. Options → Open register map file
   Note: File location <design name>/misc/Si5338/RegisterMap.txt
4. Modify settings
5. Options → save C code header files
6. Replace Header files from FSBL template with generated file

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

    };

};

Kernel

Activate:

• USB_ULPI_BUS
• RTC_DRV_ISL12022

Rootfs

Activate:

• i2c-tools

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

SI5338

File location <design name>/misc/Si5338/RegisterMap.txt

General documentation how you work with these project will be available on Si5338

Appx. A: Change History and Legal Notices

Document Change History

To get content of older revision  got to "Change History"  of this page and select older document revision number.

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Legal Notices