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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2018-11-262018.2

TE0745-test_board-vivado_2018.2-build_03_20181126115131.zip
TE0745-test_board_noprebuilt-vivado_2018.2-build_03_20181126115320.zip

John Hartfiel
  • Rework Board Part Files
  • New assembly versions
  • Rework BD Design
  • add init.sh scripts
2017-10-232017.2TE0745-test_board_noprebuilt-vivado_2017.2-build_05_20171023171903.zip
TE0745-test_board-vivado_2017.2-build_05_20171023171855.zip		John Hartfiel
  • initial release

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titleHardware Modules

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2I2i1C1c
Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
 TE0745TE0745-02-30-1I30_1i01,021GB32MB
*xc7z030 has lower MGT count
TE0745-02-30-2IA30_2i01,021GB64MB
*xc7z030 has lower MGT count
TE0745 TE0745-02-35-1C35_1c01,021GB32MB

TE0745-02-45-2I45_2i01,021GB32MB

TE0745-02-45-2IA45_2i01,021GB64MB

TE0745-02-45-1C45_1c01,02 TE0745021GB32MB

TE0745-02-45-1CA45_1c01,021GB64MB

TE0745-02-45-3EA45_3e01,021GB64MB

Design supports following carriers:

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  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode
    Note: See TRM of the Carrier and Module.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR and program PL part, 3. U-boot load Linux from SD into DDR

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  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device
    5. (optional) init.sh scripts: Scripts will enable SFP interface after linux booting, if file is copied on SD

Vivado HW Manager

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  • Add picture of HW Manager

  • add notes for the signal either groups or topics, for example:

    Control:

    • add controllable IOs with short notes..

    Monitoring:

    • add short notes for signals which will be monitored only

    SI5338_CLK0 Counter: 

    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

  • Monitoring:

    • SI5338 _CLK0 CounterCLKs: 

      • Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.
        Note: Frequency Counter is inaccurate and displayed unit is Hz        , SI5338 CLK is (0 and 3) are configured to 125MHz by default.
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System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

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*clk3 is not available on the smallest SOC (xc7z030)

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PS Interfaces

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Note:

  • optional for Zynq / ZynqMP only

  • add basic PS configuration

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titlePS Interfaces

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TypeNote
DDR
QSPIMIO
ETH0MIO
USB0MIO
SD0MIO
UART0MIO
I2C0MIO
GPIOMIO/EMIO
ETH0 ResetMIO
USB0 ResetMIO
I2C0 ResetMIO
TTC0..1EMIO
SWDT0EMIO

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