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Power and Power-On Sequence
Ethernet
There are two 100 MBit Extreme Temperature Ethernet PHY's DP83848YB on the board. Datasheet is available from TI, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board.
Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.
| ETH1 | ETH2 | Pullup | Notes | |
|---|---|---|---|---|
| CTREF | J3.57 | J3.25 | Magnetics center tap voltage | |
| TD+ | J3.58 | J3.28 | on-board | |
| TD- | J3.56 | J3.26 | on-board | |
| RD+ | J3.52 | J3.22 | on-board | |
| RD- | J3.50 | J3.20 | on-board | |
| LED1 | J3.55 | J3.23 | on-board | |
| LED2 | J3.53 | J3.21 | on-board | |
| LED3 | J3.51 | J3.19 | on-board | |
| POWERDOWN/INT | L21 | R20 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used. |
| RESET_N | M15 | R16 | on-chip | It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset). |
It is recommended to add IOB TRUE constraint for the MII Interface pins.
When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.
Power Consumption
Power Distribution Dependencies
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