Page History
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JTAG Signal | B2B Pin |
|---|---|
| TMS | JM2-12 |
| TDI | JM2-10 |
| TDO | JM2-8 |
| TCK | JM2-6 |
PS7 UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
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There are two 100 MBit Extreme Temperature Ethernet PHY's DP83848-EP provided by Texas Instrument on the board. Datasheet is provided here TI website, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. All LED outputs have on-board pull-ups. Outputs to Magnetics have also required termination resistors on board. There is no sharing of signals for the two PHY's.
PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.
Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.
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When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.
Clock Source
| IC | Description | Frequency | Used as |
|---|---|---|---|
| U14 | MEMS Oscillator | 33.3333 MHz | PS7 PLL clock |
| U5 | MEMS Oscillator | 25 MHz | Ethernet PHY Clock |
| U7 | RTC (internal oscillator) | 32.768 KHz | Used by RTC, CLKOUT of RTC not connected |
Power and Power-On Sequence
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Overview
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