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JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
JTAG Signal | B2B Pin |
|---|---|
| TMS | JM2-12 |
| TDI | JM2-10 |
| TDO | JM2-8 |
| TCK | JM2-6 |
PS7 UART
There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.
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| MIO Pin | Schematic | U13 Pin | Notes |
|---|---|---|---|
| MIO1 | SPI_CS | A1 | |
| MIO2 | SPI_DQ0/M0 | A2 | |
| MIO3 | SPI_DQ1/M1 | F6 | |
| MIO4 | SPI_DQ2/M2 | E4 | |
| MIO5 | SPI_DQ3/M3 | A3 | |
| MIO6 | SPI_SCK/M4 | A4 |
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Supply Voltage: 2.7V to 3.6V
Temperature Range:
- Industrial (-40°C to +85°C)
- Industrial Plus (-40°C to +105°C)
- Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
- Automotive AEC-Q100 Grade 2 (-40°C to +105°C)
TC I2C
The RV-3029-C3 is an ultra miniature Real-Time-Clock Module with embedded Crystal. This RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy of ± 6ppm from -40°C to +85°C and ± 8ppm from -40°C to +125°C.
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- Part number: NT5CC256M16DP Nanya
- Supply voltage: 1.35V
- Speed: 1600 Mbps
- NOR Flash
- Temperature: 0C~95C-40°C ~95°C
Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.
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The SN65HVD230Q, controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40C~125C40°C ~125°C .
| MIO Pin | Schematic | U16 Pin | Notes |
|---|---|---|---|
| MIO8 | D | 1 | |
| MIO9 | R | 4 |
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Absolute Maximum Ratings
| VIN supply voltage | 3.5 | 60 | V | TPS54260-Q1 datasheets. |
| Supply voltage for PS MIO banks | 1.71 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS MIO banks | -0.2 | VCCO_MIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for PS DDR | 1.14 | 1.89 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for PS DDR | -0.20 | VCCO_DDR + 0.20 | V | See Xilinx DS187 datasheet. |
| Supply voltage for HR I/Os banks | 1.14 | 3.465 | V | See Xilinx DS187 datasheet. |
| I/O input voltage for HR I/O banks | -0.20 | VCCIO + 0.20 | V | See Xilinx DS187 datasheet. |
| Storage Temperature | -65 | 150 | °C | See Xilinx DS187 datasheet. |
| CAN Transceiver Temperature | -40 | 125 | °C | See Texas Instrument sn65hvd230q-q1 datasheet. |
| SPI Flash Memory | -40 | 85 | °C | See Cypress S25FL127Sdatasheet. |
| DDR3 SDRAM Temperature | -40 | 95 | °C | See Nanya NT5CC256M16CP-DIA datasheet. |
Recommended Operating Conditions
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