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title	Initial delivery state of programmable devices on the module.

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Storage device name	Content	Notes
Quad SPI Flash	U13	Empty
DDR3 SDRAM	U1	Empty
24LC64	U11

Table 1: Initial state of programmable devices on delivery of the module.

Control Signals

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Overview of Boot Mode, Reset, Enables,

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Notes :

add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs

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Chip/Interface	IC	PS7 Peripheral	Notes
SPI Flash	S25FL127SABMFV10	QSPI0	16 MByte Flash
I2C EEPROM	24LC64	I2C0	64 KByte EEPROM
RTC I2C	RV-3029	I2C0
RTC Interrupt	RV-3029	GPIO - MIO0
User LED	LED Green	GPIO - MIO7

16 MByte Quad SPI Flash MemoryTable 5: On board Peripherals

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On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

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MIO Pin	Schematic	U13 Pin
MIO1	SPI_CS	A1
MIO2	SPI_DQ0/M0	A2
MIO3	SPI_DQ1/M1	F6
MIO4	SPI_DQ2/M2	E4
MIO5	SPI_DQ3/M3	A3
MIO6	SPI_SCK/M4	A4

Table 6: Quad SPI interface MIOs and pins

Supply Voltage: 2.7V to 3.6VTable 6: Quad SPI interface MIOs and pins

Temperature Range:

Industrial (-40°C to +85°C)
Industrial Plus (-40°C to +105°C)
Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
Automotive AEC-Q100 Grade 2 (-40°C to +105°C)

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The RV-3029-C3 is an ultra miniature Real-Time-Clock Module with embedded Crystal. This RTC has an I²C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy of ± 6ppm from -40°C to +85°C and ± 8ppm from -40°C to +125°C.

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MIO Pin	Schematic	U7 Pin	Notes
MIO15	SDA	5	On-board RTC, and EEPROM
MIO14	SCL	4	On-board RTC, and EEPROM

Table 7: I²C interface MIOs and pins

I^₂C EEPROM

The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

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MIO Pin	Schematic	U11 Pin	Notes
MIO15	SDA

3	On-board RTC, and EEPROM
MIO14	SCL	1	On-board RTC, and EEPROM

Table 8: I²C EEPROM interface MIOs and pins

LEDs

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Schematic	Color	Connected to	Active Level	IO Standard
D9	Green

DONE	Low	not applicable
D8	RED	MIO7	High	not applicable
D4	Green	PL pin V18	High	LVCMOS33

Table 9: On-board LEDs.

512 Mbyte DDR3L SDRAM

The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.

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Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

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Table_ETH

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title	Ethernet PHY to Zynq SoC connections.

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Schematic	ETH1	ETH2	Pullup	Notes
CTREF	J3-57	J3-25		Magnetics center tap voltage
TD+	J3-58	J3-28	on-board
TD-	J3-56	J3-26	on-board
RD+	J3-52	J3-22	on-board
RD-	J3-50	J3-20	on-board
LED1	J3-55	J3-23	on-board
LED2	J3-53	J3-21	on-board
LED3	J3-51	J3-19	on-board
POWERDOWN/INT	L21	R20	on-chip	It is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.
RESET_N	M15	R16	on-chip	It is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).

Table 10: Ethernet PHY to Zynq SoC connections.

It is recommended to add IOB TRUE constraint for the MII Interface pins.Table 10: Ethernet PHY to Zynq SoC connections.

When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.

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The SN65HVD230Q, controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40°C ~125°C .

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MIO Pin	Schematic	U16 Pin	Notes
MIO8	D	1
MIO9	R	4

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Table 11: CAN Tranciever interface MIOs

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MIO Pin	Schematic	U16 Pin	Notes
MIO8	D	1
MIO9	R	4

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Table 12: CAN Tranciever pins

Low Quiescent Current Programmable Delay Supervisory Circuit

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A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2 μF, and is fully specified SON-10 and 5 x 5 QFN-20 Packages from –40°C to 105°C for the DRC package, and from –40°C to 125°C for the RGW package.

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, and from –40°C to 125°C for the RGW package.

Clock Sources

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IC	Description	Frequency	Used as
U14	MEMS Oscillator	50 MHz	PS PLL clock
U5	MEMS Oscillator	25 MHz	Ethernet PHY Clock
U7	RTC (internal oscillator)	32.768 KHz	Used by RTC, CLKOUT of RTC not connected

Table 13: Oscillators.

Power and Power-On Sequence

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Power supply with minimum current capability of 3.5 A for system startup is recommended.

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for system startup is recommended.

Power Consumption

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Power Input Pin	Typical Current
VIN	TBD*

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* TBD - To Be Determined

Power Distribution Dependencies

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Figure 3: Power Distribution Dependencies

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The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.

Voltage Monitor Circuit

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_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.

Voltage Monitor Circuit

Power Rails

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Power Rail Name	B2B Connector JM1 Pin	B2B Connector JM2 Pin	B2B Connector JM3 Pin	Direction
VIN	1,3	-	-	Input
VMIO	-	2	-	I/O
3.3V	19	4	25,57	Output
1.8V	-	5	-	Output

Table 14: Module power rails.

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Bank Voltages

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Bank	Schematic Name	Voltage	Notes
500	VCCO_MIO0_500	3.3V
501	VCCO_MIO1_500	3.3V
502	VCCO_DDR_502	1.5V
13 HR	VCCO_13	3.3V	Supplied by the carrier board. JM1
33 HR	VCCO_33	3.3V	Supplied by carrier board. JM3
34 HR	VCCO_34	3.3V
35 HR	VCCO_35	3.3V	Supplied by the carrier board. JM2,JM3

Table 15: Zynq SoC bank voltages.

Board to Board Connectors

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3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)
Operating Temperature:-55°C ~ 125°C
Current Rating: 2.6A per ContactNumber of Positions: 80
Number of Rows: 2

Absolute Maximum Ratings

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per ContactNumber of Positions: 80
Number of Rows: 2

Absolute Maximum Ratings

Processing System(PS)

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Symbols	Description	Min	Max	Unit
VCCPINT	PS internal logic supply voltage	-0.5	1.1	V
VCCPAUX	PS auxiliary supply voltage	-0.5	2.0	V
VCCPLL	PS PLL supply	-0.5	2.0	V
VCCO_DDR	PS DDR I/O supply voltage	-0.5	2.0	V
VPREF	PS input reference voltage	-0.5	2.0	V
VCCO_MIO0	PS MIO I/O supply voltage for HR I/O banks	-0.5	3.6	V
VCCO_MIO1	PS MIO I/O supply voltage for HR I/O banks	1.71	3.45	V

Table 16: PS absolute maximum ratings.

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Programmable Logic(PL)

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Symbols	Description	Min	Max	Unit
VCCINT	PL internal logic supply voltage	-0.5	1.1	V
VCCPAUX	PL auxiliary supply voltage	-0.5	2.0	V
VCCPLL	PL PLL supply	-0.5	1.1	V
VPREF	PL input reference voltage	-0.5	2.0	V
VCCO	PL supply voltage for HR I/O banks	-0.5	3.6	V
VIN	I/O input voltage for HR I/O banks	1.71	3.45	V

Table 16: PL absolute maximum ratings.

Technical Specifications

Absolute Maximum Ratings

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	3.5	60	V	TPS54260-Q1 datasheets.
Supply voltage for PS MIO banks	1.71	3.465	V	See Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks	-0.2	VCCO_MIO + 0.20	V	See Xilinx DS187 datasheet.
Supply voltage for PS DDR	1.14	1.89	V	See Xilinx DS187 datasheet.
I/O input voltage for PS DDR	-0.20	VCCO_DDR + 0.20	V	See Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks	1.14	3.465	V	See Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks	-0.20	VCCIO + 0.20	V	See Xilinx DS187 datasheet.
Storage Temperature	-65	150	°C	See Xilinx DS187 datasheet.
CAN Transceiver Temperature	-40	125	°C	See Texas Instrument sn65hvd230q-q1 datasheet.
SPI Flash Memory	-40	85	°C	See Cypress S25FL127S datasheet.
DDR3 SDRAM Temperature	-40	95	°C	See Nanya NT5CC256M16CP-DIA datasheet.

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Industrial and automotive grade: -40°C to +85°C.Operating temperature range depends also on customer design and cooling solution. Please contact us for options.85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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Parameter	Min	Max	Units	Reference Document
VIN supply voltage	3.5	60	V	TPS54260-Q1 datasheets.
Supply voltage for PS MIO banks	1.71	3.465	V	See Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks	-0.2	VCCO_MIO + 0.20	V	See Xilinx DS187 datasheet.
Supply voltage for PS DDR	1.14	1.89	V	See Xilinx DS187 datasheet.
I/O input voltage for PS DDR	-0.20	VCCO_DDR + 0.20	V	See Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks	1.14	3.465	V	See Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks	-0.20	VCCIO + 0.20	V	See Xilinx DS187 datasheet.
Storage Temperature	-65	150	°C	See Xilinx DS187 datasheet.

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CAN Transceiver Temperature	-40	125	°C	See Texas Instrument sn65hvd230q-q1 datasheet.
SPI Flash Memory	-40	85	°C	See Cypress S25FL127S datasheet.
DDR3 SDRAM Temperature	-40	95	°C	See Nanya NT5CC256M16CP-DIA datasheet.

Physical Dimensions

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Trenz Electronic Documentation

Versions Compared

Old Version 116

New Version 117

Key

Control Signals

Low Quiescent Current Programmable Delay Supervisory Circuit

Clock Sources

Power and Power-On Sequence

Power Consumption

Power Distribution Dependencies

Voltage Monitor Circuit

Voltage Monitor Circuit

Power Rails

Board to Board Connectors

Absolute Maximum Ratings

Absolute Maximum Ratings

Processing System(PS)

Absolute Maximum Ratings