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Template Revision 2.3

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"


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Table of Contents

Table of Contents

Overview

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Notes :

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

Within the complete module only Automotive components are installed.

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

Key Features

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    • Note:
    • Xilinx XA7Z020-1CLG484Q (Automotive)
    • Rugged for shock and high vibration
    • Dimensions: 6 x 6 cm
    • Temperature range: Automotive
    • Dual-Core ARM Cortex-A9 MPCore
    • 2 x 100 MBit Ethernet transceiver (PHY)
    • 512 MByte DDR3L SDRAM, 16-bit-wide 
    • 16 MByte QSPI Flash memory (with XiP support)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
    • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
    • CAN transceiver (PHY)
    • 12 V power supply with watchdog
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
    • Temperature compensated RTC (real-time clock)
    • Three user LEDs
    • Evenly-spread supply pins for good signal integrity

      Other assembly options for cost or performance optimization plus high volume prices available on request.

      Depending on the customer design, additional cooling might be required.

Block Diagram

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Main Components

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  • Add List below


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  1. 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver  DP83848, U3
  4. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
  5. Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
  6. 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
  7. Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
  8. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
  9. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
  10. 100 MBit Ethernet transceiver  DP83848MPHPEP, U10
  11. 64 Kbit I2C EEPROM, 24LC64, U11
  12. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
  13. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
  14. Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
  15. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
  16. CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
  17. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM2
  18. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM3
  19. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
  20. User LED Green

Initial Delivery State

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Storage device name

Content

Notes

Quad SPI Flash

U13

Empty

DDR3 SDRAMU1Empty
24LC64U11



Control Signals

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  • Overview of Boot Mode, Reset, Enables,


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MODE Signal State

Boot Mode

High or open

QSPI



Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:


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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13JM148VCCO_13
500JM143.3V
33JM3343.3V
35JM3203.3V
35JM2223.3V
501JM238VMIO1MIO1 VREF is connected to resistor divider to support HSTL18


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJM2-12
TDIJM2-10
TDOJM2-8
TCKJM2-6


PS7 UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Chip/InterfaceICPS7 PeripheralNotes
SPI FlashS25FL127SABMFV10QSPI016 MByte Flash
I2C EEPROM24LC64I2C064 KByte EEPROM
RTC I2CRV-3029I2C0
RTC InterruptRV-3029GPIO - MIO0
User LEDLED GreenGPIO - MIO7


16 MByte Quad SPI Flash Memory

On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.


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MIO PinSchematicU13 PinNotes
MIO1SPI_CSA1
MIO2SPI_DQ0/M0A2
MIO3SPI_DQ1/M1F6
MIO4SPI_DQ2/M2E4
MIO5SPI_DQ3/M3A3
MIO6SPI_SCK/M4A4



Supply Voltage: 2.7V to 3.6V

 Temperature Range:

  • Industrial (-40°C to +85°C)
  • Industrial Plus (-40°C to +105°C)
  • Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
  • Automotive AEC-Q100 Grade 2 (-40°C to +105°C)

RTC I2C

The RV-3029-C3 is an ultra miniature Real-Time-Clock Module with embedded Crystal. This RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy of ± 6ppm from -40°C to +85°C and ± 8ppm from -40°C to +125°C.


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MIO PinSchematicU7 PinNotes
MIO15SDA5On-board RTC, and EEPROM
MIO14SCL4On-board RTC, and EEPROM


I2C EEPROM

The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.


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MIO PinSchematicU11 PinNotes
MIO15SDA3On-board RTC, and EEPROM
MIO14SCL1On-board RTC, and EEPROM


LEDs

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SchematicColorConnected toActive LevelIO Standard
D9GreenDONELownot applicable
D8REDMIO7Highnot applicable
D4GreenPL pin V18HighLVCMOS33


512 Mbyte DDR3L SDRAM

The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: NT5CC256M16DP Nanya
  • Supply voltage: 1.35V
  • Speed: 1600 Mbps
  • NOR Flash
  • Temperature: -40°C ~95°C 

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet  DP83848-EP are provided by Texas Instrument on the board. Datasheet is provided TI website, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.


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SchematicETH1ETH2PullupNotes
CTREFJ3-57J3-25
Magnetics center tap voltage
TD+J3-58J3-28on-board
TD-J3-56J3-26on-board
RD+J3-52J3-22on-board
RD-J3-50J3-20on-board
LED1J3-55J3-23on-board
LED2J3-53J3-21on-board
LED3J3-51J3-19on-board
POWERDOWN/INTL21R20on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.
RESET_NM15R16on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).



It is recommended to add IOB TRUE constraint for the MII Interface pins.

When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.

CAN Transceiver

The SN65HVD230Q,  controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40°C ~125°C .


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MIO PinSchematicU16 PinNotes
MIO8D1
MIO9R4


Low Quiescent Current Programmable Delay Supervisory Circuit

The TPS3808G01-Q1 microprocessor supervisory circuits monitor system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the useradjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

The TPS3808G01-Q1 device uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be useradjusted from 1.25 ms to 10 s by connecting the CT pin to an external capacitor. The TPS3808G01-Q1 has a very low typical quiescent current of 2.4 μA, so it is well suited for battery-powered applications. 

Low Dropout Linear Regulator

The TPS74801-Q1 low-dropout (LDO)  provides an easy-to-use robust power management  solution for a wide variety of applications. User programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well- suited for powering many different types of Monitoring or Provides a Sequencing Signal processors and ASICs. The enable input and power for Other Supplies good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing Voltage Startup requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2 μF, and is fully specified SON-10 and 5 x 5 QFN-20 Packages from –40°C to 105°C for the DRC package, and from –40°C to 125°C for the RGW package.

Clock Sources

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ICDescriptionFrequencyUsed as
U14MEMS Oscillator50 MHzPS PLL clock
U5MEMS Oscillator25 MHzEthernet PHY Clock
U7RTC (internal oscillator)32.768 KHzUsed by RTC, CLKOUT of RTC not connected


Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3.5 A for system startup is recommended.

Power Consumption

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Power Input PinTypical Current
VINTBD*



* TBD - To Be Determined

Power Distribution Dependencies

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Power-On Sequence

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The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.

Voltage Monitor Circuit


Power Rails

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B2B Name

B2B

JM1 Pin

B2B

JM2 Pin

B2B

JM3 Pin

DirectionNotes
VIN1,3--InputSupply voltage from carrier board.
VCCO_1339--I/O
VBATT-1-Output
3.3V192, 425,57OutputInternal 3.3V voltage level.

1.8V

-5-OutputInternal 1.8V voltage level.


Bank Voltages

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Bank          

Schematic Name

Voltage

Notes
500VCCO_MIO0_5003.3V
501

VCCO_MIO1_500

3.3V
502VCCO_DDR_5021.5V
13 HRVCCO_13 3.3VSupplied by the carrier board. JM1
33 HRVCCO_333.3VSupplied by carrier board. JM3
34 HRVCCO_343.3V


35 HRVCCO_353.3V

Supplied by the carrier board. JM2,JM3


Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

  • 3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)

    Operating Temperature:-55°C ~ 125°C
    Current Rating: 2.6A per ContactNumber of Positions: 80
    Number of Rows: 2

Technical Specifications

Absolute Maximum Ratings

Processing System(PS)

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SymbolsDescriptionMinMaxUnit
VCCPINTPS internal logic supply voltage-0.51.1V
VCCPAUXPS auxiliary supply voltage-0.52.0V
VCCPLLPS PLL supply-0.52.0V
VCCO_DDRPS DDR I/O supply voltage-0.52.0V
VPREFPS input reference voltage-0.52.0V
VCCO_MIO0PS MIO I/O supply voltage for HR I/O banks-0.53.6V
VCCO_MIO1PS MIO I/O supply voltage for HR I/O banks1.713.45V


Programmable Logic(PL)

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SymbolsDescriptionMinMaxUnit
VCCINTPL internal logic supply voltage-0.51.1V
VCCPAUXPL auxiliary supply voltage-0.52.0V
VCCPLLPL PLL supply-0.51.1V
VPREFPL input reference voltage-0.52.0V
VCCOPL supply voltage for HR I/O banks-0.53.6V
VINI/O input voltage for HR I/O banks1.713.45V



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ParameterMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.2VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.
I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.
Storage Temperature-65150°CSee Xilinx DS187 datasheet.
CAN Transceiver Temperature-40125°CSee Texas Instrument sn65hvd230q-q1 datasheet.
SPI Flash Memory-4085°CSee Cypress S25FL127S datasheet.
DDR3 SDRAM Temperature-4095°C

See Nanya NT5CC256M16CP-DIA datasheet.


Recommended Operating Conditions

Commercial grade: 0°C to +70°C.

Industrial and automotive grade: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.


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ParameterMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.2VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.
I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.
Storage Temperature-65150°CSee Xilinx DS187 datasheet.
CAN Transceiver Temperature-40125°CSee Texas Instrument sn65hvd230q-q1 datasheet.
SPI Flash Memory-4085°CSee Cypress S25FL127S datasheet.
DDR3 SDRAM Temperature-4095°C

See Nanya NT5CC256M16CP-DIA datasheet.


Physical Dimensions

  • Module size: 60 mm × 60 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 7 mm.

  • PCB thickness: 1.6 mm.

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Variants Currently In Production

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Trenz shop TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

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DateRevisionNotePCNDocumentation Link
-01Prototypes--






Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Document Change History

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    • Metadata is only used of compatibility of older exports


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  • change list

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Disclaimer

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