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PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

Scroll Title
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titleEthernet PHY to Zynq SoC connections

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SchematicETH1ETH2PullupNotes
CTREFJ3-57J3-25
Magnetics center tap voltage
TD+J3-58J3-28on-board
TD-J3-56J3-26on-board
RD+J3-52J3-22on-board
RD-J3-50J3-20on-board
LED1J3-55J3-23on-board
LED2J3-53J3-21on-board
LED3J3-51J3-19on-board
POWERDOWN/INTL21R20on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.
RESET_NM15R16on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).

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CAN Transceiver

Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 

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