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Zynq-7020SoC includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (PSRST_POR_BOUT) and the system reset signal (PS_SRST_B) which is connected to VMIO, it means after power on the system will be reset.
| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | PinPS_POR_B | 500 | B5 | JM2-9 | PS_SRST_B | 501 | C9 | JM2-2| I/O | Note |
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Reset | J2-7 | Input | Comes from Carrier | | RST_OUT | J2-9 | Out |
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Signals, Interfaces and Pins
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| Scroll Title |
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| anchor | Table_OBP_CAN |
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| title | CAN Tranciever interface MIOs |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
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| MIO Pin | Schematic | Pin | Notes |
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| MIO8 | D | U16-1 | Driver Input | | MIO9 | R | U16-4 | Reciever Output |
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Low Dropout Linear Regulator
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