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Zynq-7020SoC includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (RST_OUT) Reset) connected to carrier and the system reset signal (PS_SRST_B) which is connected to VMIO, it means after power on the system PS will be reset.
| Scroll Title |
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| anchor | Table_OV_RST |
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| title | Reset process. |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Signal | B2B | I/O | Note |
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Reset | J2-7 | Input | Comes from Carrier | | RST_OUT | J2-9 | Out |
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Signals, Interfaces and Pins
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| Scroll Title |
|---|
| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| style | |
|---|
| widths | |
|---|
| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
|---|
| 13 | JM1J1 | 48(24) | VCCO_13 | variable from carrier | | 500 | JM1J1 | 4 | 3.3V |
| | 501 | J2 | 37 | VMIO1 | variable from carrier | | 33 | JM3J3 | 34 | 3.3V |
| | 35 | JM3J3 | 20 | 3.3V |
| | 35 | JM2J2 | 22 | 3.3V |
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JTAG Interface
JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.
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