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Scroll Title
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titleInitial delivery state of programmable devices on the module

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Storage

device name

Device

Symbol

Content

Quad SPI Flash

U13

Not Programmed

EEPROMU11Not Programmed


Control Signals

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  • Overview of Boot Mode, Reset, Enables,

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Scroll Title
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titleBoot process.

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E4

Signal

FPGA BankPinB2BSignal StateBoot Mode


Boot_R


500


E4


J2-11

Low

QSPI

Boot_R500

J2-11
HighSD Card


Reset

Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B)  connected to VMIO, it means after power on the PS will be reset.

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SPI_DQ3/M3
Scroll Title
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titleMIOs pins

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MIO PinSchematicNotes
MIO0MIO0RTC interrupt
MIO1SPI_CSSPI Flash
MIO2-5SPI_DQ0
/M0
SPI Flash
MIO3SPI_DQ1/M1SPI Flash
MIO4SPI_DQ2/M2SPI Flash
MIO5
-3/M0-3SPI Flash
MIO6SPI_SCK/M4SPI Flash clock
MIO7LED REDLED
MIO8DCAN Transceiver
MIO9RCAN Transceiver
MIO10IO_0JM1-7
MIO11IO_1JM1-9
MIO12IO_2JM1-11
MIO13IO_3JM1-13
MIO14SCLEEPROM
MIO15SDAEEPROM
MIO16-MIO53PS_MIOxxBank 501


UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

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