Page History

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Template Revision 2.3

TRM Name always "TE Series Name" +TRM, for example "TE0720 TE0728 TRM"

HTML

<!-- tables have all same width (web max 1200px and pdfPDF full page(640px), flexible width or fix width on menu for single column can be used as before) -->
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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image Image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf PDF export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables
Scroll Title
anchor Table_tablename
title Text
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths
sortByColumn 1
sortEnabled false
cellHighlighting true
Example Comment
1 2

The anchors of the Scroll Title should be named consistant across TRMs. A An incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>#<anchor name>
Refer to Anchror Anchor from external : <page url>#<pagename URL>#<page name without space characters>-<anchorname><anchor name>

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL): for example:https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Scroll pdf ignore

Table of Contents

Table of Contents

Overview

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips.

Within the complete module only Automotive components are installed.

All this in a compact 6 x 6 cm form factor, at the most competitive price.The Trenz Electronic TEB0728 Carrier Board provides functionalities for testing, evaluation and development purposes of company's 6 x 6 cm SoMs. The Carrier Board is equipped with various components and connectors for different configuration setups. See "6 x 6 SoM" Carriers" page for more information about 6 x 6 cm SoMs.

Refer to http://trenz.org/te0728TEB0728-info for the current online version of this manual and other available documentation.

Key Features

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- Note:

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Block Diagram

Samtec Tiger Eye Terminal Socket ( 80 pins, 2 rows)
Micro SD card socket
3 User LEDs, Red, Yellow, Green
Two RJ45 Gigabit Ethernet socket
Trenz 6x6 module connector strips (3 x Samtec Tiger Eye series connectors)
Barrel Jack for 5V power supply
One user push button

Block Diagram

scrollscroll-title

anchor	Figure_OV_BD
title	TE0728 TEB0728 block diagram

Scroll Ignore
Scroll Only

Main Components

hiddenidComments

draw.io Diagram

viewerToolbar
border	false

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fitWindow	false

diagramDisplayName

Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below


lbox	true
revision	17
diagramName	TE0728_BD1
simpleViewer	false
width
links	auto
tbstyle	hidden
diagramWidth	641

Scroll Only
Image Added

Main Components

Page properties

hidden	true
id	Comments

Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Scroll Title

anchor	Figure_OV_MC
title	TEB0728 main components

Scroll Ignore

draw.io Diagram

border	false

Scroll Title

anchor	Figure_OV_MC
title	TE0728 main components

Scroll Only

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true
scroll-epub	true
scroll-html	true

draw.io Diagram

border	true
viewerToolbar	true

fitWindow	false
diagramDisplayName
lbox	true
revision	21
diagramName	TE0728_MC
simpleViewer	false
widthdiagramWidth
links	auto641
tbstylerevision	hidden	3
diagramWidth	642

Scroll Only
Image Added

User push-button, S1
Jumper (Boot Mode), J4
External connector (VG96) placeholder, J5 / J6Board to Board Connector, J1-J2-J3
LEDs , D1
CR1220 Backup-Battery holder, B1
SD Card Connector, J10
Board to Board Connector, J1-J2-J3
RJ45 Gigabit Ethernet connector, J7-J8
User push-button, S1
Jumper, J4
XMOD JTAG- / UART-header, JB1
Barrel jack for 5V Barrel jack for power supply, J9
Jumper Jumper(VCCIO_13), J11
CR1220 Backup-Battery holder, B1

Initial Delivery State

There is no hardware component to be programmed on the carrier.

Scroll Title

anchor	Table_OV_IDS
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes	Quad SPI Flash	Not Programmed	DDR3 SDRAM	Not Programmed	RTC	Not Programmed

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Configuration Signals

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Overview of Boot Mode, Reset, Enables,

Boot Process

Scroll Title

anchor	Table_OV_BP
title	Boot process.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

MODE Signal State	Boot Mode
High or open	QSPI

...

Designator	B2B	Jumper	Boot Mode
Boot_R	J4	J2-11	Open	QSPI
Boot_R	J4	J2-11	Short	SD Card

There is a user push button which is used for RESET signal.

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Notes :

For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- SD
- USB
- ETH
- FMC
- ...
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title

anchor	Table_SIPOV_B2BBP
title	General PL I/O to B2B connectors informationReset process.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

FPGA Bank ConnectorVoltage Notes

Signal	Designator		B2B		Active	I/O Signal Count	Level
RESET

JTAG Interface

JTAG access to the Xilinx XXXXXXX FPGA through B2B connector JM2.

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anchor	Table_SIP_JTG
title	JTAG pins connection

S1

J2-7

Active High

Signals, Interfaces and Pins

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...

JTAG Signal

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B2B Pin

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Notes :

add For carrier or stand-alone boards use subsection for every component which is important for design, connector type (add designator on description, not on the subsection title), for example:
- Two 100 Mbit Ethernet Transciever PHYSD
- USB PHY
- Programmable Clock GeneratorETH
- Oscillators
- eMMCs
- RTC
- FTDI
- FMC
- ...
- DIP-Switches
- Buttons
- LEDs
For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
- JTAG
- UART
- I2C
- MGT
- ...

Board to Board (B2B) I/Os

Number of I/O signals FPGA bank numbers connected to the B2B connectors:

Scroll Title

anchor	Table_SIP_B2B
title	General overview of PL I/O signals and SoM's interfaces connected to the B2B connectors.

Scroll Title

anchor	Table_OBP
title	On board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface

IC

PS7 Peripheral

Notes

...

B2B Connector	Interfaces	Number of I/O	Notes
J1	User I/O	48 singel ended, 24 differential	Connected to Bank 13
	User I/O	4 Single ended	MIO10...13
	CANH , CANL	2 single ended	MIO8, MIO9
J2	User I/O	22 singel ended, 11 differential
	User I/O	38 single ended	MIO16...53
	SoM Control Signals	5	RESET, RST_OUT, BOOT_R,
	JTAG Interface	4	TCK , TDO, TDI, TMS
J3	User I/O	20 Single ended, 10 differential	Connected to Bank 35
	User I/O	34 single ended, 17 differential	Connected to Bankd 33
	Ethernet 1	4 single ended, 2 differential	ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3
	Ethernet 2	4 single ended, 2 differential	ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3

On-board Connector

There are two pin placeholder on the board, J5-J6.

On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

...

anchor	Table_OBP_SPI
title	Quad SPI interface MIOs and pins

...

U7 Pin

Scroll Title

anchor	Table_OBPSIP_RTCOnB
title	I2C interface MIOs and pinsGeneral information about On-board connectors information

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

VGA96 Vertical Connector	Interfaces	Number of I/O

MIO Pin

Schematic

	Notes

SDASCL

anchor	Table_OBP_ETH
title	Ethernet PHY to Zynq SoC connections

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 4

New Version Current

Key

Overview

Key Features

Block Diagram

Block Diagram

Main Components

Main Components

Initial Delivery State

Configuration Signals

Boot Process

Board to Board (B2B) I/Os

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

On-board Connector

EEPROM

JTAG Interface Base

Ethernet

SD Card Socket

CAN Transceiver

Low Quiescent Current Programmable Delay Supervisory Circuit

Low Dropout Linear Regulator

RJ45 Connector

Power Supply

Power Consumption

Power Distribution Dependencies

On-board Peripherals

Push button

Power-On Sequence

Jumpers

Absolute Maximum Ratings

Processing System(PS)

LEDs

Power and Power-On Sequence

Power Supply

Power Rails

Board to Board Connectors

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer