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Template Revision 2.3

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

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          • "OBP" for On board Peripherals,
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Table of Contents

Table of Contents

Overview

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Notes :

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive Zynq-7020 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

Within the complete module only Automotive components are installed.

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

Key Features

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    • Note:
    • Xilinx XA7Z020-1CLG484Q (Automotive)
    • Rugged for shock and high vibration
    • Dimensions: 6 x 6 cm
    • Temperature range: Automotive
    • Dual-Core ARM Cortex-A9 MPCore
    • 2 x 100 MBit Ethernet transceiver (PHY)
    • 512 MByte DDR3L SDRAM, 16-bit-wide 
    • 16 MByte QSPI Flash memory (with XiP support)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
    • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
    • CAN transceiver (PHY)
    • 12 V power supply with watchdog
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
    • Temperature compensated RTC (real-time clock)
    • Three user LEDs
    • Evenly-spread supply pins for good signal integrity

Depending on the customer design, additional cooling might be required.

Block Diagram

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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


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titleTE0728 main components


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  1. 512 MByte DDR3 SDRAM, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver, U3
  4. Standard Clock Oscillators @ 25MHz, U5
  5. 1.5 A Low Dropout Linear Regulator, U6
  6. Real Time Clock, Micro Crystal @32.768 MHz, U7
  7. 100 MBit Ethernet transceiver, U10
  8. 64 Kbit I2C EEPROM, U11
  9. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, U12
  10. 16 MByte QSPI Nor Flash memory, U13
  11. Standard Clock Oscillators @ 50MHz, U14
  12. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, U15
  13. CAN Tranceiver, U16
  14. B2B connector , JM2
  15. B2B connector , JM3
  16. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
  17. User LED Green

Initial Delivery State

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Storage Device

Symbol

Content

Quad SPI Flash

U13

Not Programmed

EEPROMU11Not Programmed


Control Signals

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  • Overview of Boot Mode, Reset, Enables,

Boot Mode

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Signal

FPGA BankPinB2BSignal StateBoot Mode

Boot_R

500

E4

J2-11

Low

QSPI

HighSD Card


Reset

Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B)  connected to VMIO, it means after power on the PS will be reset.

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Signal

B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13J148(24)VCCO_13variable from carrier
500J143.3V
501J237VMIO1variable from carrier
33J3343.3V
35J3203.3V
35J2223.3V


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6


MIO Pins

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MIO PinSchematicNotes
MIO0MIO0RTC interrupt
MIO1SPI_CSSPI Flash
MIO2-5SPI_DQ0-3/M0-3SPI Flash
MIO6SPI_SCK/M4SPI Flash clock
MIO7LED REDLED
MIO8DCAN Transceiver
MIO9RCAN Transceiver
MIO10IO_0J1-7
MIO11IO_1J1-9
MIO12IO_2J1-11
MIO13IO_3J1-13
MIO14SCLEEPROM
MIO15SDAEEPROM
MIO16-MIO53PS_MIOxx



On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Chip/InterfaceProductNotes
SPI FlashU1316 MByte Flash
EEPROMU1164 Kbit EEPROM
RTCU7Real Time Clock
DDR3 SDRAMU1Volatile Memory
EthernetU3, U10Two 100 Mbit Ethernet
CAN TransceiverU16
User LEDD4Green LED


Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.


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MIO PinSchematicPinNotes
MIO1SPI_CSU13-A1
MIO2SPI_DQ0/M0U13-A2
MIO3SPI_DQ1/M1U13-F6
MIO4SPI_DQ2/M2U13-E4
MIO5SPI_DQ3/M3U13-A3
MIO6SPI_SCK/M4U13-A4


RTC 

The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC intruppt is connected to MIO0 connected to Bank 500, pin G6.


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MIO PinSchematicPinNotes
MIO15SDAU7-5On-board RTC, and EEPROM
MIO14SCLU7-4On-board RTC, and EEPROM


EEPROM

The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

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MIO PinSchematicPinNotes
MIO15SDAU11-3On-board RTC, and EEPROM
MIO14SCLU11-1On-board RTC, and EEPROM


LEDs

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SchematicColorConnected toActive LevelIO Standard
D9GreenDONELownot applicable
D8REDMIO7Highnot applicable
D4GreenBank 33 - V18HighLVCMOS33


DDR3 SDRAM

The TE0728 SoM has two 512 MByte volatile DDR3 SDRAM IC for storing user application code and data.

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrument on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

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SchematicETH1ETH2PullupNotes
CTREFJ3-57J3-25
Magnetics center tap voltage
TD+J3-58J3-28on-board
TD-J3-56J3-26on-board
RD+J3-52J3-22on-board
RD-J3-50J3-20on-board
LED1J3-55J3-23on-board
LED2J3-53J3-21on-board
LED3J3-51J3-19on-board
POWERDOWN/INTL21R20on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.
RESET_NM15R16on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).


CAN Transceiver

Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 


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MIO PinSchematicPinNotes
MIO8DU16-1Driver Input
MIO9RU16-4Reciever Output


Low Dropout Linear Regulator

The low-dropout (LDO)  provides an easy-to-use robust power management  solution for a wide variety of applications. User programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well- suited for powering many different types of Monitoring or Provides a Sequencing Signal processors. The enable input and power for Other Supplies good output allow easy sequencing with external regulators. 

Clock Sources

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titleOsillators

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ICDescriptionFrequencyUsed as
U14MEMS Oscillator50 MHzPS PLL clock
U5MEMS Oscillator25 MHzEthernet PHY Clock
U7RTC (internal oscillator)32.768 KHzUsed by RTC, CLKOUT of RTC not connected


Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3.5 A for system startup is recommended.

Power Consumption

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power on Sequence

The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. 

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Power Distribution Dependencies

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Voltage Monitor Circuit

The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.

Power Rails

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B2B Name

B2B

JM1 Pin

B2B

JM2 Pin

B2B

JM3 Pin

DirectionNotes
VIN1,3--InputSupply voltage from carrier board.
VCCO_1339--I/O
VBATT-1-OutputRTC Supply voltage
3.3V192, 425,57OutputInternal 3.3V voltage level.

1.8V

-5-OutputInternal 1.8V voltage level.


Bank Voltages

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Bank          

Schematic Name

Voltage

HR I/O BankNotes
500VCCO_MIO0_5003.3VSupported
501

VCCO_MIO1_500

Variable

502VCCO_DDR_5021.5VSupported
13 HRVCCO_13 Variable
Supplied by the carrier board. J1
33 HR3.3V3.3VSupportedSupplied by carrier board. J3
34 HR3.3V3.3VSupported


35 HR3.3V3.3VSupported

Supplied by the carrier board. J2, J3


Board to Board Connectors

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  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

Include Page
PD:6 x 6 SoM LSHM B2B Connectors
PD:6 x 6 SoM LSHM B2B Connectors

6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

  • 3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)

Technical Specifications

Absolute Maximum Ratings

Processing System(PS)

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SymbolsDescriptionMinMaxUnit
VCCPINTPS internal logic supply voltage-0.51.1V
VCCPAUXPS auxiliary supply voltage-0.52.0V
VCCPLLPS PLL supply-0.52.0V
VCCO_DDRPS DDR I/O supply voltage-0.52.0V
VPREFPS input reference voltage-0.52.0V
VCCO_MIO0PS MIO I/O supply voltage for HR I/O banks-0.53.6V
VCCO_MIO1PS MIO I/O supply voltage for HR I/O banks1.713.45V



Programmable Logic(PL)

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SymbolsDescriptionMinMaxUnit
VCCINTPL internal logic supply voltage-0.51.1V
VCCPAUXPL auxiliary supply voltage-0.52.0V
VCCPLLPL PLL supply-0.51.1V
VPREFPL input reference voltage-0.52.0V
VCCOPL supply voltage for HR I/O banks-0.53.6V
VINI/O input voltage for HR I/O banks1.713.45V


Recommended Operating Conditions

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.2VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.
I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.
Storage Temperature-45125°CSee Xilinx DS187 datasheet.


Temprature range: -40°C to +85°C.

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Physical Dimensions

  • Module size: 60 mm × 60 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 7 mm.

  • PCB thickness: 1.6 mm.

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Variants Currently In Production

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Trenz shop TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

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DateRevisionNotePCNDocumentation Link
-01Prototypes--






Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Document Change History

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