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Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information

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FPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotes
13J148(24)VCCO_13variable from carrier
500J143.3V
501J237VMIO1variable from carrier
33J3343.3V
35J3203.3V
35J2223.3V


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DDR3 SDRAM

The TE0728 SoM has two 512 MByte volatile DDR3 SDRAM IC for storing user application code and data.

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrument on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

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Scroll Title
anchorTable_OBP_CAN
titleCAN Tranciever interface MIOs

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MIO PinSchematicPinNotes
MIO8DU16-1Driver Input
MIO9RU16-4Reciever Output

Low Dropout Linear Regulator

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Clock Sources

Scroll Title
anchorTable_OBP_CLK
titleOsillators

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ICDescriptionFrequencyUsed as
U14MEMS Oscillator50 MHzPS PLL clock
U5MEMS Oscillator25 MHzEthernet PHY Clock
U7RTC (internal oscillator)32.768 KHzUsed by RTC, CLKOUT of RTC not connected


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