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anchor	Table_SIP_B2B
title	General PL I/O to B2B connectors information

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FPGA Bank	Type	B2B Connector	I/O Signal Count	Voltage Level	Notes
13	HR	J1	48(24)	VCCO_13	variable from carrier
500	HR	J1	4	3.3V
501	HR	J2	37	VMIO1	variable from carrier
33	HR	J3	34	3.3V
35	HR	J3	20	3.3V
35	HR	J2	22	3.3V

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.

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anchor	Table_SIP_B2B_Eth
title	Ethernet PHY B2B connectors.

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Schematic	ETH1	ETH2	Direction	Pullup	Notes
CTREF	J3-57	J3-25	In		Magnetics center tap voltage
TD+	J3-58	J3-28	Out	on-board	Transfer
TD-	J3-56	J3-26	Out	on-board
RD+	J3-52	J3-22	In	on-board
RD-	J3-50	J3-20	In	on-board
LED1	J3-55	J3-23	Out	on-board
LED2	J3-53	J3-21	Out	on-board
LED3	J3-51	J3-19	Out	on-board
POWERDOWN/INT	L21	R20	In	on-chip
RESET_N	M15	R16	In	on-chip	Active low PHY Reset

CAN pins connections to Board to Board (B2B).

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anchor	Table_SIP_B2B_CAN
title	CAN B2B connectors.

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Schematic	B2B	Voltage LevelMIO Pin	Notes
CANH/CANL	J1-2	3.3V	CANL	/J1-4	-
TX/RX		MIO8/MIO93.3V

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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anchor	Table_OBP_MIOs
title	MIOs pins

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