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Template Revision 2.3

TRM Name always "TE Series Name" +TRM, for example "TE0720 TRM"


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable
  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

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Table of Contents

Table of Contents

Overview

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Notes :

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating an Automotive Xilinx  Zynq-7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , DDR3L SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

Within the complete module only Automotive components are installed.

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

Key Features

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    • Note:
    • Xilinx XA7Z020-1CLG484Q (Automotive) [Z7014S is available on demand]
    • Rugged for shock and high vibration
    • Dimensions: 6 x 6 cm
    • Temperature range: Automotive
    • Dual-Core ARM Cortex-A9 MPCore
    • 2 x 100 MBit Ethernet transceiver (PHY)
    • DDR3L SDRAM, 16-bit-width [ ]
    • QSPI Flash memory (with XiP support) [ ]
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
    • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
    • CAN transceiver (PHY)
    • 12 V power supply with watchdog
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
    • Temperature compensated RTC (real-time clock)
    • Three user LEDs
    • Evenly-spread supply pins for good signal integrity

Depending on the customer design, additional cooling might be required.

Block Diagram

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titleTE0728 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


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titleTE0728 main components


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  1. DDR3 SDRAM, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver, U3
  4. 100 MBit Ethernet transceiver, U10
  5. User LED Green, D4
  6. Real Time Clock, Micro Crystal , U7
  7. Standard Clock Oscillators, U5
  8. 64 Kbit I2C EEPROM, U11
  9. CAN Tranceiver, U16
  10. QSPI Nor Flash memory, U13
  11. Standard Clock Oscillators, U14
  12. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
  13. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  14. B2B connector , JM2
  15. B2B connector , JM3
  16. B2B connector , JM1

Initial Delivery State

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titleInitial delivery state of programmable devices on the module

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Storage Device

Symbol

Content

Quad SPI Flash

U13

Not Programmed

EEPROMU11Not Programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables,

Boot Mode

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Signal

FPGA BankPinB2BSignal StateBoot Mode

Boot_R

500

E4

J2-11

Low

QSPI

HighSD Card


Reset

Zynq-7020SoC  includes a reset that is driven by the reset system. Hardware resets are driven by the power-on reset signal (Reset) connected to carrier and the system reset signal (PS_SRST_B)  connected to VMIO, it means after power on the PS will be reset.

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titleReset process.

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Signal

B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
13HRJ148 Single-end, 24 DiffVCCO_13variable from carrier
500MIOJ143.3V
501MIOJ237VMIO1variable from carrier
33HRJ3343.3V
35HRJ3203.3V
35HRJ2223.3V



Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.

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titleEthernet PHY B2B connectors.

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SchematicETH1ETH2DirectionPullupNotes
CTREFJ3-57J3-25In
Magnetics center tap voltage
TD+J3-58J3-28Outon-boardTransfer
TD-J3-56J3-26Outon-board
RD+J3-52J3-22Inon-boardRecieve
RD-J3-50J3-20Inon-board
LED1J3-55J3-23Outon-boardLED Yellow on carrier
LED2J3-53J3-21Outon-board
LED3J3-51J3-19Outon-boardLED Green on carrier
POWERDOWN/INTL21R20Inon-chip
RESET_NM15R16Inon-chipActive low PHY Reset


CAN PHY

CAN pins connections to Board to Board (B2B).

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SchematicB2BMIO PinDirectionNotes
CANH/CANLJ1-2/J1-4-Inout/Inout
TX/RX
MIO8/MIO9Out/In



JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6


MIO Pins

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titleMIOs pins

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MIO PinSchematicB2BNotes
MIO0MIO0-RTC interrupt
MIO1...MIO6

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

-SPI Flash
MIO7LED RED-LED
MIO8/MIO9Tx/Rx-CAN Transceiver
MIO10...MIO13IO_0 ... IO_3J1GPIO
MIO14/MIO15SCL/SDA-I2C
MIO16...MIO27-J2GPIO
MIO28...MIO39

Tx_clk, Txd0...Txd3, Tx_ctl

Rx_clk, Rxd0...Rxd3, Rx_ctl

J2ETH
MIO40...MIO48CLK, Cmd, Data0...Data3, wp, cdJ2SD
MIO48MIO48J2LED Red on Carrier
MIO49MIO49J2LED Yellow on Carrier
MIO50MIO50J2LED Green on Carrier
MIO51MIO51J2GPIO
MIO52/MIO53UART_Txd / UART_RxdJ2UART transfer/recieve



On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Chip/InterfaceProductNotes
QSPI FlashU13---
EEPROMU11EEPROM
RTCU7Real Time Clock
DDR3 SDRAMU1Volatile Memory
EthernetU3, U10Two 100 Mbit Ethernet PHY
CAN TransceiverU16
User LEDD4Green LED


Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.


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titleQuad SPI interface MIOs and pins

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MIO PinSchematicPinNotes
MIO1SPI_CSU13-A1
MIO2SPI_DQ0/M0U13-A2
MIO3SPI_DQ1/M1U13-F6
MIO4SPI_DQ2/M2U13-E4
MIO5SPI_DQ3/M3U13-A3
MIO6SPI_SCK/M4U13-A4


RTC 

The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC intruppt is connected to MIO0 connected to Bank 500 through pin G6.

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titleI2C interface MIOs and pins

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MIO PinI2C AddressDesignatorNotes
MIO14...150x68U7---



EEPROM

The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

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titleI2C interface MIOs and pins

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MIO PinI2C AddressDesignatorNotes
MIO14...150xA0U11---



LEDs

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SchematicColorConnected toActive LevelIO Standard
D9GreenDONELownot applicable
D8REDMIO7Highnot applicable
D4GreenBank 33 - V18HighLVCMOS33


DDR3 SDRAM

The TE0728 SoM has a volatile DDR3 SDRAM IC for storing user application code and data. Size of DDR3 can be varied in different assembly versions. 

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrument on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

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titleEthernet PHY to Zynq SoC connections

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SchematicETH1ETH2PullupNotes
CTREFJ3-57J3-25
Magnetics center tap voltage
TD+J3-58J3-28on-board
TD-J3-56J3-26on-board
RD+J3-52J3-22on-board
RD-J3-50J3-20on-board
LED1J3-55J3-23on-boardLED Yellow on Carrier - ACK
LED2J3-53J3-21on-boardSpeed
LED3J3-51J3-19on-boardLED Green on Carrier- Link
POWERDOWN/INTL21R20on-chip
RESET_NM15R16on-chip


CAN Transceiver

Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 


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titleCAN Tranciever interface MIOs

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MIO PinSchematicPinNotes
MIO8D - TxU16-1Driver Input
MIO9R - RxU16-4Reciever Output



Clock Sources

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titleOsillators

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ICDescriptionFrequencyUsed as
U14MEMS Oscillator50 MHzPS_CLK
U5MEMS Oscillator25 MHzEthernet PHY Clock
U7RTC (internal oscillator)32.768 KHzCLKOUT of RTC is not connected


Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2.5A for system startup is recommended.

Power Consumption

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titlePower Consumption

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power on Sequence

The TE07028 SoM meets the recommended criteria to power up the Xilinx Zynq properly by keeping a specific sequence of enabling the on-board DC-DC converters and regulators dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.

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titlePower On Sequence


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Power Distribution Dependencies

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Voltage Monitor Circuit

The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.


Power Rails

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titleModule power rails.

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B2B Name

B2B

JM1 Pin

B2B

JM2 Pin

B2B

JM3 Pin

DirectionNotes
VIN1,3--InputSupply voltage from carrier board.
VCCO_1339--I/O
VBATT-1-OutputRTC Supply voltage
3.3V19425,57OutputInternal 3.3V voltage level.
VMIO

-

2
Input3.3V from carrier

1.8V

-5-OutputInternal 1.8V voltage level.


Bank Voltages

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titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

HP I/O BankNotes
500VCCO_MIO0_5003.3VSupported
501

VCCO_MIO1_501

2.5V or 3.3VSupportedsupplied by 3.3V from carrier.
502VCCO_DDR_5021.5VSupported
13VCCO_131.8V or 3.3VSupportedSupplied by the carrier board. J1
333.3V3.3VSupportedSupplied by carrier board. J3
343.3V3.3VSupported


353.3V3.3VSupported

Supplied by the carrier board. J2, J3


Board to Board Connectors

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  • This section is optional and only for modules.
  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

    Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

Include Page
PD:6 x 6 SoM LSHM B2B Connectors
PD:6 x 6 SoM LSHM B2B Connectors

6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

  • 3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)

Technical Specifications

Absolute Maximum Ratings


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SymbolsDescriptionMinMaxUnit
VCCPINTPS internal logic supply voltage-0.51.1V
VCCPAUXPS auxiliary supply voltage-0.52.0V
VCCPLLPS PLL supply-0.52.0V
VCCO_DDRPS DDR I/O supply voltage-0.52.0V
VPREFPS input reference voltage-0.52.0V
VCCO_MIO0PS MIO I/O supply voltage for HR I/O banks-0.53.6V
VCCO_MIO1PS MIO I/O supply voltage for HR I/O banks1.713.45V
VCCINTPL internal logic supply voltage-0.51.1V
VCCPAUXPL auxiliary supply voltage-0.52.0V
VCCPLLPL PLL supply-0.51.1V
VPREFPL input reference voltage-0.52.0V
VCCOPL supply voltage for HR I/O banks-0.53.6V
VINI/O input voltage for HR I/O banks1.713.45V



Recommended Operating Conditionse

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.2VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.
I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.
Storage Temperature-40+85°C
Operating Temperature-40+125°CWithout the flash memory S25FL127S


Physical Dimensions

  • Module size: 60 mm × 60 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 7 mm.

  • PCB thickness: 1.6 mm.

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Variants Currently In Production

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Trenz shop TE0728 overview page
English pageGerman page


Revision History

Hardware Revision History

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DateRevisionNotePCNDocumentation Link

 

04Product ReleasePCNTE0728-04-1Q

 

03Prototype-TE0728-03-1Q


Hardware revision number is printed on the PCB board next to the module model number separated by the dash.

Document Change History

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following
    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports


Scroll Title
anchorTable_RH_DCH
titleDocument change history.

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
typeFlat
showVersionsfalse


Page info
infoTypeModified by
typeFlat
showVersionsfalse

  • change list

--

all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --


Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices