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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| style | |
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| widths | |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| FPGA Bank | | B2B Connector | Interfaces | Number of I/O |
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Signal Count | Notes |
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J1
| User I/O | 48 singel ended, 24 differential 2 singel ended | Connected to Bank 13 | 48 singel ended, 24 differential 2 singel ended | Connected to Bank 12 | | JTAG Interface | 5 single ended | TCK, TDI, TMS, TDO | | SFP+ Connector | 8x LVDS pairs | SPF0....7_RX_N/P , SPF0....7_TX_N/P | J2
| User I/O | 22 singel ended, 11 differential |
| | 38 single ended | MIO16...53 | | SoM Control Signals | 5 | RESET, RST_OUT, BOOT_R, | | JTAG Interface | 4 | TCK , TDO, TDI, TMS | J3
| User I/O | 20 Single ended, 10 differential
| Connected to Bank 35 | | 34 single ended, 17 differential | Connected to Bankd 33 | | Ethernet 1 | 4 single ended, 2 differential | ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3 | | Ethernet 2 | 4 single ended, 2 differential | ETH_CTREF , ETH_TD+, ETH_TD- , ETH_RD+, ETH_RD-, ETH_LED1, ETH_LED2, ETH_LED3 |
Voltage Level | Notes
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JTAG Interface
JTAG access to the TExxxx SoM through B2B connector JMX.
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