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Table of Contents

Table of Contents

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The Trenz Electronic TEI0016 is an a commercial-grade module based on Intel® MAX 10. Intel MAX 10 devices are the ideal solution for system management, I/O expansion, communication control planes, industrial, automotive, and consumer applications.

Refer to http://trenz.org/tei0016-info for the current online version of this manual and other available documentation.

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Note:
Use 'Key Features' description in shoping page, for example: https://shop.trenz-electronic.de/de/TE0728-04-1Q-SoC-Micromodul-mit-Xilinx-Automotive-Zynq-7020-512-MByte-DDR3L-6-x-6-cm

  • Intel® MAX 10 Commercial [10M08SAU169C8G]

    • Package: UBGA-169

      -UBGA

    • Speed Grade: C8 (Slowest)

    • Temperature:

       0°C ~ 85°C

       0°C to 85°C

    • Package compatible device 10M08...10M16 as assembly variant on request possible

  • SDRAM Memory up to

    64Mb, 166MHz

    32 Mbyte (8Mbyte default)

  • USB 2.0

    Dual High Speed USB to

    Multipurpose UART/FIFO IC

  • Quad SPI Flash, 64Mb

  • (FT2232H)

    • 4 Kbit EEPROM Memory for FTDI configuration data
    • Micro USB Receptacle (communication and power)

  • SPI Flash - NOT INSTALLED (only special option)

    EEPROM Memory, 4Kb

  • 8x User LED 

  • Micro USB

    port

    Connector

  • 18 16 Bit Analog to Digital Converter with 1 MSPS or 500 kSPS

  • 2x SMA Female Connector

  • I/O interface: 23x GPIO

  • Power Supply: 5V (from USB)

  • Dimension: 25 mm x 86.5 mm

  • Others:

    • Instrumentation Amplifier

    • Differential Amplifier

    • Operational

    Others:

    • Dimension: 86m x 25m

    • Instrumentation Amplifier

    • Voltage Feedback

      Amplifier

Block Diagram

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titleTEI0016 block diagram


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borderfalse
viewerToolbartrue
fitWindowfalse
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lboxtrue
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simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth641


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titleTEI0016 main components


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borderfalse
viewerToolbartrue
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simpleViewerfalse
width
linksauto
tbstylehidden
diagramWidth639641


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  1. SMA Connector, J5...6
  2. Instrumentation Amplifier, U12
  3. Analog to Digital ConvertorConverter, U6
  4. Voltage Reference, U8
  5. Voltage Regulator, U10 - U13 - U16
  6. Buck Switching Voltage Regulator/LDO, U11 - U4
  7. SDRAM Memory, U2
  8. Intel® MAX 10 FPGA, U1
  9. SPI Flash Memory, U5 (not populated)
  10. 12.00 MHz MEMS oscillatorOscillator 12MHz, U7
  11. FTDI USB to JTAG/UART convertor/FIFO, U3
  12. User LEDs, D2...9
  13. 4Kb EEPROM, U9
  14. Configuration LED (Red) , D10
  15. Power-on LED (Green), D1
  16. SwitchPush button, S1...2
  17. Micro USB portConnector, J9
  18. 1x14 pin header, J2 (Not assembled)
  19. 1x6 pin header, J4 Pin Holder (Not assembled), J1...4
  20. Jumper, J3
  21. 1x14 pin header, J1 (Not assembled)

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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Not Programmed

Storage device name

Content

Notes

Quad SPI Flash

N/A

Not

Programmed

populated

EEPROMProgrammed

FTDI configuration

SDRAM


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or (using a *.POF file) on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile configuration memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up. To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile (using a *.SOF file), means the configuration is lost after power off.

Reset process must be done FPGA Reconfigration can be triggered by pressing push button S1.

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titleReset process.

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Signal

Push ButtonPin HeaderNote

RESET

S1J2connected Connected to nCONFIG


Signals, Interfaces and Pins

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FPGA BankI/O Signal CountConnected toNotes
Bank 1A71x14 Pin header, J1AIN0...6
1Jumper, J3AIN7
Bank 1B51x6 Pin header, J4JTAG_EN, TDI, TDO, TMS, TCK
Bank 2


41x14 Pin header, J1D2...5
5A2DADC, U15ADC_EN, ADC_SDI, ADC_SDO, ADC_SCK, ADC_CNV
112MHz Oscillator, U7CLK12M
2Amplifier, U12nIAMP_A0, nIAMP_A1
Bank 322SDRAM, U2RAM_ADDR_CMD
Bank 59

1x14 Pin header, J2

DIO6...14
21x14 Pin header, J1DIO0...1
1D12_RDIO12
Bank 616SDRAM, U2DQ0...15
2SDRAM, U2DQM0...1
1D11_RDIO11
Bank 8



8User Red LEDs, D2...9LED0...7
6SPI Flash, U5F_CS, F_CKCLK, F_DI, F_DO, nSTATUS, DEVCLRn
1Red LED, D10CONF_DONE
6FTDI JTAG/UART Adapter, U3BDBUS0...5
1Push Button, S2USER_BTN

JTAG Interface


Micro-USB Connector

The Micro-USB2 connector J9 provides an interface to access the UART and JTAG functions via FTDI FT2232 chip. The use of this feature requires that USB driver is installed on your host PCJTAG access to the TEI0015 SoM through pin header connector J4.

Pin Header Connector
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PinsConnected to

JTAG Signal

Note
TMSJ4-6TDIJ4-5TDOJ4-4TCK

J4-3

JTAG_ENJ4-2

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

VBUSUSB_VBUS
D+FTDI U3, DP pin
D-FTDI U3, DM pin


JTAG Interface

JTAG access to the TEI0016 SoM through pin header connector J4.

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JTAG Signal

Pin Header Connector

Note
TMSJ4-6
TDIJ4-5
TDOJ4-4
TCK

J4-3


JTAG_ENJ4-2Pulled-up to 3.3V.


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


Analog to Digital Convertor
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Chip/InterfaceDesignatorNotes
77530151U2
FTDI FT2232HU3JTAG/UART/FIFO
77530151U5
77530151U9
OscillatorU712 MHz clock source
77530151U6Analog to Digital Converter
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Chip/InterfaceDesignatorNotes
SDRAMU2
FTDI FT2232HU3JTAG/UART Adapter
SPI Flash MemoryU5EEPROMU9
OscillatorU712MHz clock source
A2D ConvertorU6
8x User LEDsD2...9Red LEDs
Push ButtonsS1...2


SDRAM

TEI0015 TEI0016 is equipped with a Winbond 64 MBit (8 MByte) SDRAM chip in standard configuration, variants with 256 Mbit (32 MByte) memory density are also available. The SDRAM chip is connected to the FPGA bank 3 and 6 via 16-bit memory interface with 166MHz clock frequency and CL3 CAS latency..

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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titleSDRAM interface IOs and pins

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SDRAM I/O Signals

Signal Schematic Name

Connected toNotes
Address inputs

A0 ... A13

bank 3-
Bank address inputs

BA0 / BA1

bank 3

-
Data input/output

DQ0 ... DQ15

bank 6

-
Data mask

DQM0 ... DQM1

bank 6

-
ClockCLKbank 3-
Control Signals

CS

bank 3

Chip select

CKE

bank 3

Clock enable

RAS

bank 3

Row Address Strobe

CAS

bank 3

Column Address Strobe

WEbank 3Write Enable


FTDI FT2232H

The FTDI chip U3 converts signals from USB2 USB to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity features of the FT2232H chip.
FTDI FT2232H chip channel A is used in MPPSE mode for JTAG, 6 I/O's of . Channel B are routed to FPGA bank 8 of the FPGA SoC and are usable for example as GPIOs, UART or other standard interfaces.is configured to be used as in async FIFO mode, this is default mode when using preprogrammed FTDI configuration. In this mode the communication from host PC looks like normal UART but from the FTDI side it is 8 bit FIFO style interface.

The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.The configuration of FTDI FT2232H chip is pre-programmed on the EEPROM U9.

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titleFTDI chip interfaces and pins

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FTDI Chip U3 PinSignal Schematic NameConnected toNotes
ADBUS0TCKFPGA bank 1B, pin G2JTAG interface
ADBUS1TDIFPGA bank 1B, pin F5
ADBUS2TDOFPGA bank 1B, pin F6
ADBUS3TMS

FPGA bank 1B, pin G1

BDBUS0BDBUS0FPGA bank 8, pin A4user User configurable
BDBUS1BDBUS1FPGA bank 8, pin B4user User configurable
BDBUS2BDBUS2FPGA bank 8, pin B5user User configurable
BDBUS3BDBUS3FPGA bank 8, pin A6user User configurable
BDBUS4BDBUS4FPGA bank 8, pin B6user User configurable
BDBUS5BDBUS5FPGA bank 8, pin A7user configurable

SPI Flash Memory

On-board serial configuration memory (U5) is provided by Winbond with 64 MBit (8 MByte) storage capacity. This non volatile memory is used to store initial FPGA configuration via JTAG interface. The memory is connected to FPGA bank 8 via SPI interface.

User configurable
BDBUS6BDBUS6FPGA bank 6, pin C11
BDBUS7BDBUS7FPGA bank 3, pin J7
BCBUS0BCBUS0FPGA bank 5, pin J9
BCBUS1BCBUS1FPGA bank 3, pin K5
BCBUS2BCBUS2FPGA bank 3, pin K5
BCBUS3BCBUS3FPGA bank 3, pin K5
BCBUS4BCBUS4FPGA bank 3, pin K5


SPI Flash

Optional SPI flash device maybe assembled in custom variants, normally it is not populated.

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titleQuad SPI Flash memory interface

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titleQuad SPI Flash memory interface

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Signal Schematic NameConnected toNotes
F_CSFPGA bank 8, pin B3chip Chip select
F_CLKFPGA bank 8, pin A3clockClock
F_DIFPGA bank 8, pin A2data Data in / out
nSTATUS

FPGA bank 8, pin C4

data Data in / out, configuration dual-purpose pin of FPGA
DEVCLRNFPGA bank 8, pin B9data Data in / out, configuration dual-purpose pin of FPGA
F_DOFPGA bank 8, pin B2data Data in / out


EEPROM

The configuration of FTDI FT2232H chip is pre-programmed on in the EEPROM U9.

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SchematicConnected toNotes

EECS

FTDI U3, Pin EECS
EECLKFTDI U3, Pin EECLK
EEDATAFTDI U3, Pin EEDATA

A2D Convertor

The TEI0010 board is equipped with the Analog Devices AD4003BCPZ, 18-bit A2D converter (ADC).

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anchorTable_OBP_A2D
titleA2D converter interface and pins

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IN+

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ADC

The boards with article nuber - TEI0016-03-08-C8A - are equipped with the Analog DevicesADC - ADAQ7988BCCZ - 16-bit 500kSPS,
boards wit article number TEI0016-03-08-C8B are equipped with the Analog Devices ADC - ADAQ7980BCCZ - 16-bit 1MSPS.

The ADC can be distinguished via its part code:

  • TEI0016-03-08-C8A: ADAQ7988BCCZ - 16-bit 500kSPS - starts with Y6H
  • TEI0016-03-08-C8B: ADAQ7980BCCZ - 16-bit 1.0MSPS - starts with Y6F
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titleTEI0016 part code variants


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bordertrue
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diagramNameTEI0016_part-code-variants
simpleViewerfalse
width600
diagramWidth1922
revision1


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Designator
Pins
Color
Connected to
Active Level
Notes
NoteD2...9RedLED1...8Active HighUser LEDsD10RedCONF_DONEActive LowConfiguration DONE LEDD1Green3.3V Power RailActive HighAfter power on it will be on